On a recent run of prototypes using the nRF9151 and the nPM1300 we've had a few failure where the nRF9151 cannot connect to the debugger and the board exhibits much higher current draw (110mA) versus the ones the were able to be programmed (10mA). We have narrowed down the high current draw going into the VDD pin of the nRF9151 on the failed boards.
These boards were visually inspected and electrically tested (flying probe) prior to being powered for programming and nothing looked out of the ordinary. Power was provided by a 50mA current limited 4.2V supply through the VBAT pin of the nPM1300 (which also provides a regulated 1.8V for the VDD_GPIO domain), which passes that out through VSYS and to VDD of the nRF9151. I was told that the 3 failed boards exhibited the high current immediately upon applying 4.2V to VBAT and am trying to figure out why this could have happened.
There are a couple of theories, but I want to confirm if one aspect of the design could possibly be the cause. The nRF9151 DEC0 pin is decoupled with 4.7uF on the development kit. The HW design guidelines say "An external capacitor improves the stability of the internal supply. The voltage level of DEC0 is approximately 2.2 V."
What is the acceptable range of capacitance that can be used on DEC0? More specifically, would using a 10uF 10V X5R instead of a 4.7uF 10V X5R cause any issues?
What else could possibly cause the nRF9151 to fail upon power up for the first time?