nRF9151 DEC0 capacitance

On a recent run of prototypes using the nRF9151 and the nPM1300 we've had a few failure where the nRF9151 cannot connect to the debugger and the board exhibits much higher current draw (110mA) versus the ones the were able to be programmed (10mA). We have narrowed down the high current draw going into the VDD pin of the nRF9151 on the failed boards.

These boards were visually inspected and electrically tested (flying probe) prior to being powered for programming and nothing looked out of the ordinary. Power was provided by a 50mA current limited 4.2V supply through the VBAT pin of the nPM1300 (which also provides a regulated 1.8V for the VDD_GPIO domain), which passes that out through VSYS and to VDD of the nRF9151. I was told that the 3 failed boards exhibited the high current immediately upon applying 4.2V to VBAT and am trying to figure out why this could have happened.

There are a couple of theories, but I want to confirm if one aspect of the design could possibly be the cause. The nRF9151 DEC0 pin is decoupled with 4.7uF on the development kit. The HW design guidelines say "An external capacitor improves the stability of the internal supply. The voltage level of DEC0 is approximately 2.2 V."

What is the acceptable range of capacitance that can be used on DEC0? More specifically, would using a 10uF 10V X5R instead of a 4.7uF 10V X5R cause any issues?

What else could possibly cause the nRF9151 to fail upon power up for the first time?

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  • Hi,

    The capacitor on DEC0 must be 4.7uF, as this is a decoupling for the internal regulator, not following the values in the reference design will result in unexpected behavior.

     

    Power was provided by a 50mA current limited 4.2V supply through the VBAT pin of the nPM1300 (which also provides a regulated 1.8V for the VDD_GPIO domain), which passes that out through VSYS and to VDD of the nRF9151.

    50mA supply for to the nRF9151 is not enough, the maximum current draw of the nRF9151 is close to 500mA(worst case, transmitting at maximum output power) so a 50mA supply will result in the nRF9151 resetting due to the voltage dropping on the VDD net.

     

    Best regards,

    Bendik

  • Hi Bendik. Thanks for the quick response.

    Typically regulators have a range of acceptable output capacitance to maintain stability. Just looking to understand what range of capacitance will actually maintain stability. Surely that internal data is available?

    Further, with a 2.2V bias the actual capacitance of the ceramic X5R cap will drop. The 10uF 20% 10V X5R Murata GRM155R61A106ME11D we are using will actually be closer to 5.0uF with a 2.2V bias. The 4.7uF 20% 10V X5R Murata GRM155R61A475MEAAD used on the nRF9151 DK will also be closer to 3.4uF nominal with a 2.2V bias.

    Is the actual capacitance difference of ~1.6uF really enough to potentially cause the internal regulator to become unstable? Both caps have a resistance under 100mOhm from 3kHz to 400MHz.

    The 50mA limit was just for the initial power up and programming steps. From the batch of boards that was programmed successfully, it looked like less than 50mA was required for erasing and programming. A much higher current limit is obviously required for full functionality, but we're just in the initial bring up phase.

    Brian

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  • Hi Bendik. Thanks for the quick response.

    Typically regulators have a range of acceptable output capacitance to maintain stability. Just looking to understand what range of capacitance will actually maintain stability. Surely that internal data is available?

    Further, with a 2.2V bias the actual capacitance of the ceramic X5R cap will drop. The 10uF 20% 10V X5R Murata GRM155R61A106ME11D we are using will actually be closer to 5.0uF with a 2.2V bias. The 4.7uF 20% 10V X5R Murata GRM155R61A475MEAAD used on the nRF9151 DK will also be closer to 3.4uF nominal with a 2.2V bias.

    Is the actual capacitance difference of ~1.6uF really enough to potentially cause the internal regulator to become unstable? Both caps have a resistance under 100mOhm from 3kHz to 400MHz.

    The 50mA limit was just for the initial power up and programming steps. From the batch of boards that was programmed successfully, it looked like less than 50mA was required for erasing and programming. A much higher current limit is obviously required for full functionality, but we're just in the initial bring up phase.

    Brian

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  • Hi Nordic team. I've received emails that an engineer has been assigned to this post but am still waiting for a response.

    I really just need to know for certain if using the 10uF 10V X5R cap (which is actually about 5uF with 2.2V DC bias) on DEC0 is acceptable for production circuits.

    Brian

  • Hi Brian,

    Apologies for the long delay getting back to you.

     

    DEC0 is decoupling for the main internal power rail for the nRF9151 SiP.  In addition to the external decoupling capacitor there are internal ones inside the SiP. We have observed internally that a high capacitance(47uF) on the DEC0 results in the nRF9151 failing to power up.

    10uF may be on the limit, causing only some of the boards to no power up properly.

     

    All of our verification and testing of the nRF9151 have been done with 4.7uF on DEC0, we can only guarantee that the nRF9151 will function correctly with 4.7uF on the DEC0 pin. So for production we recommend sticking to 4.7uF as specified in the reference schematic in the nRF9151 Hardware Design Guidelines.

     

    Best regards,

    Bendik

  • Thank you Bendik.

    Knowing that there are additional internal caps makes more sense to keep the external cap value lower. We will change the 10uF cap to a 4.7uF for production.

    Brian

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