Where to find DT Overlay errors?

[Seth_Kazarians]

I'm setting up a board I just built in NCS, and I made an overlay file for it.  Specifically, I am setting up the UART21 peripheral and assigning pin outputs.  I made a mistake of assigning the wrong pins for UART21 (P2.08 and P2.09 rather than P2.07 and P2.08).  

I thought to just try out my pin configuration in the overlay file, and see if it'll work.  NCS builds it, flashes it, and the code runs.  But there is no indication that anything is wrong besides the UART output not actually going anywhere.  As in, there isn't a compile time error, nor a run-time error.  Is this expected?

Also, why is there a PSEL register at all if there is only 1 valid value for the pin?

DevZone AI response follow up:  The AI suggested that I can set UARTE21 pins to any pins within P1.  I tried this but none of them actually output any serial data like I got on P2.08.  II also tried setting UARTE21.TXD to P2.02 as that's on the datasheet dedicated function list, but that doesn't work.  

Here is the overlay file:

/ {
	aliases {
		ledonboard = &led_debug_0;
	};

	leds {
		compatible = "gpio-leds";

		led_debug_0: led_0 {
			gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
		};
	};
};

&pinctrl {
	uart21_default: uart21_default {
		group1 {
			psels = <NRF_PSEL(UART_TX, 2, 2)>;
		};

		group2 {
			psels = <NRF_PSEL(UART_RX, 2, 0)>;
			bias-pull-up;
		};
	};

	uart21_sleep: uart21_sleep {
		group1 {
			psels = <NRF_PSEL(UART_TX, 2, 2)>,
				<NRF_PSEL(UART_RX, 2, 0)>;
			low-power-enable;
		};
	};
};

&uart21 {
	status = "okay";
	current-speed = <115200>;
	pinctrl-0 = <&uart21_default>;
	pinctrl-1 = <&uart21_sleep>;
	pinctrl-names = "default", "sleep";
};

Another thing I observed is that the `psels` fields in the `zephyr.dts` file would only have 1 of the 2 pins set as connected (the leading bit of the psel register).  Is this expected?

[Nishant Gaurav]

Hi seth,

thanks for posting this issue here,

1. Valid pins for UARTE21

Either:

• Any pins on Port 1 (P1.00–P1.15), or
• The dedicated cross-domain pins on Port 2: TX = P2.08, RX = P2.07

2. Why no build error

NRF_PSEL() just bit-packs function, port and pin into a 32-bit value. Nothing in devicetree validates that the peripheral can physically route to that pin.

3. Why no runtime error

The pinctrl driver writes the value into PSEL and configures the GPIO, then returns 0. No check. UARTE TX is fire-and-forget — EasyDMA runs, ENDTX fires, driver reports success. The chip has no way to know if the line goes anywhere.

4. The "leading bit" in zephyr.dts

Not a connect bit — it's the function ID in the upper byte. TX is function 0, RX is function 1:

NRF_PSEL(UART_TX, 2, 8) -> 0x00000048
NRF_PSEL(UART_RX, 2, 7) -> 0x01000047

5. fix

Same overlay, but with the pins changed to the only valid P2 pair:

psels = <NRF_PSEL(UART_TX, 2, 8)>;   /* TX = P2.08 */
psels = <NRF_PSEL(UART_RX, 2, 7)>;   /* RX = P2.07 */

Plus constant latency.

On NCS 3.3.x — prj.conf only, no code:

CONFIG_SOC_NRF_FORCE_CONSTLAT=y

zephyr/soc/nordic/common/nrf_constlat.c requests it for you at SYS_INIT(PRE_KERNEL_1).

On NCS 3.0.0 — SOC_NRF_FORCE_CONSTLAT doesn't exist yet, so request it yourself:

CONFIG_NRF_SYS_EVENT=y

#include <nrf_sys_event.h>

nrf_sys_event_request_global_constlat();



thanks and regards
Nishant