EasyDMA memory location __at__ fails

[Mary]

NCS SDK 3.4.0
NRF54LM20DK

The nRF54LM20A data sheet warns against using the same RAM subordinate by more than one bus manager.  From section 4.2.1,

Avoid situations where more than one bus manager is accessing the same RAM subordinate

There is an example for how to set up an EasyDMA transfer in section 4.2.2.1.

READERBUFFER_SIZE 5
WRITERBUFFER_SIZE 6
uint8_t readerBuffer[READERBUFFER_SIZE] __at__ 0x20000000;
uint8_t writerBuffer[WRITERBUFFER_SIZE] __at__ 0x20000005;
// Configuring the READER channel
MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &readerBuffer;
// Configure the WRITER channel
MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;
MYPERIPHERAL->WRITER.PTR = &writerBuffer;

However, if I add the buffer declaration to my project, the compiler gives an error.  It does not recognize the __at__ directive.

Why are you giving an example that doesn't compile with your tools?

How does one actually specify a particular RAM location for a buffer in order to avoid the conflict between bus managers?

Mary

[Mary]

And I forgot to ask,

What are the addresses of RAMa, RAMb, and RAMc so that I can ensure that the buffers are in different RAM subordinates?

[Turbo J]

Check the docs, the infrastructure for a variable in a fixed RAM location is non-trivial for GCC and Zephyr. You would need to define a section in the DTS and reference it in code - which would obscure the RAM location here.

The sample is intended as pseudo code, but it may actually work in some other compilers (like IAR or keil).

The actual RAM locations for those variables are important here to understand the chapter below in the manual properly. You should never need that in your application code - let the linker figure out those adresses for you.

[Mary]

Ok, but how do I tell the linker that bufferA and bufferB need to be in different RAM subordinates?

[Turbo J]

If you really want to look at sample code, compile a BTLE sample for the NRF5340 SoC and look how the shared SRAM section is set up in the DTS (finished files under build subfolder). The dual core uses that for core-to-core communication.

The basic idea is to reserve RAM space in the DTS and put the buffers into that section. 

But I would only consider that in case I ran into actual EasyDMA performance problems.