nRF52 pin muxing

[Matts]

Hi.

I've searched this forum and also the code for pin muxings. One of post here said that any gpio can be configured for any output. However how is this done in code? And how the p0.20 names map to names used in the config?

Currently we are trying to configure SPI 0 to for following lines:

 Pin#   Pin_name   Signal_name
 23       P0.20            RST (reset)
 27       P0.22            CS (chip select)
 28       P0.23            DATA (MOSI)
 37       P0.27            CLK   (Clock)

In code I can see config like this:

#define SSD1306_CONFIG_VDD_PIN      2
#define SSD1306_CONFIG_CLK_PIN      23
#define SSD1306_CONFIG_MOSI_PIN     24
#define SSD1306_CONFIG_CS_PIN       22
#define SSD1306_CONFIG_DC_PIN       20
#define SSD1306_CONFIG_RST_PIN      19

Does the above SSD1306_CONFIG_CLK_PIN 23 map to pin numbers here (on the die outlines): infocenter.nordicsemi.com/.../pin.html

[Matts]

Ok, so after little iteration I got this figured out. So the number after P0. is the pin number used in the configurations.

As a sidenote it would be quite beneficial to have some sort of guide to platform configuration.