SPI - one clock cycle missing?

[senses]

Hi,

My settings are: NRF_DRV_SPI_FREQ_1M, NRF_DRV_SPI_MODE_2, NRF_DRV_SPI_BIT_ORDER_MSB_FIRST.

I'm trying to readback 0xD8. The proper value should be 0x71. Instead, I'm getting 0xB8. If I understand MODE 2 correctly, I'm doing the following: "SCK active low, sample on rising edge of clock." If I follow the rising edges, I should be getting 0x71 but the first MOSI byte is 0xB0 instead of 0xD8. Can someone help?

[RK]

Looking at the arrows on the trace you've attached the Salae is set up to sample on the falling edge of the clock, which is why it's showing 0xB8. And that is Mode 2, clock active low, data captured on the leading edge which is falling, not rising.