Interrupt during ISR

[Markus Mueller]

Hi,

we use the GPIOTE to get informed if the value of a GPIO pin gets from hi to low.

If this happens, the GPIOTE event handler will be called.

What will happen, if the value of the GPIO pin gets back to hi and again to low during the process of the GPIOTE event handler?

[Susheel Nuguru]

If the condition for the interrupt is true again while processing the same interrupt, then the interrupt will be pended to NVIC. Read more about the NVIC pend register here

Since there is only one pending bit per interrupt source, if this condition is true more than once while (or before) processing that interrupt, then the new interrupt will set the pending bit on an already set bit which effectively means the last interrupt(s) which were pended are lost.

But if only one interrupt of the same source happen during processing, then it will not be lost as it is saved in the pended state of NVIC register.

[Markus Mueller]

"But if only one interrupt of the same source happen during processing, then it will not be lost as it is saved in the pended state of NVIC register."

So this means, if the process of the first interrupt is done, a second interrupt is processed because of the pended state of NVIC register?

[Susheel Nuguru]

that depends .. the second interrupt in the pended state will be processed immediately after the first one only if there are no other interrupts with higher priority pended. Else the higher priority interrupts will be processed first and then when they are completed then the second one which we were talking about would be be cleared from pended state and processed

[Susheel Nuguru]

This text might be intersting for you

A pending interrupt remains pending until one of the following: The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then: For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive.