According to the User Guide,
After each byte has been sent over the TXD line, a TXDRDY event will be generated.
When all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have been transmitted, the
UARTE transmission will end automatically and an ENDTX event will be generated.
Are the above events generated when the stop bit of the last byte is transmitted? Or are these events generated as soon as the last byte is shifted out of internal HW shift register (6-byte internal HW FIFO)?
If we have a strict time requirement to set a IO line immediately (within 10 micro secs) after sending the last byte, is that possible? What kind of latency to be expected between the stop bit of the last byte and ENDTX event published? We plan to use 1M BAUD.