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nRF51822, max IO pin voltage while off?

Frank Zhao

To be more detailed:

One of my ADC pins will be connected to another device that could be providing a voltage of about 3V, but through a 100 kohm resistor. (actually it's 6V, with two 100 kohm resistors as a divider)

While the nRF chip's VDD is completely off, the other device will not be off.

Is this safe long term? I don't want to leak any current.

If it is unsafe, I have another solution that will cost two extra MOSFETs, but I'd rather save money.

Thanks

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    As you can see in table 13 of the PS, doing this would violate the specification, since the I/O pin voltage would be above VDD+0.3 V (VDD being 0 in your case, but the I/O being 3 V). The exact effect of this is unknown, but this is not something I'd recommend you to test.

    Depending on your application, I would consider to leave the nRF51822 continously powered, but just set it in system off when not needed, not actually turn it off. If you do, and have VDD > 2.7 V, you are also allowed to have 3 V on a pin all the time. The chip is supposed to consume < 1 µA in this mode, but due to a PAN, current revisions might consume more. This will be fixed in the upcoming revision.

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    As you can see in table 13 of the PS, doing this would violate the specification, since the I/O pin voltage would be above VDD+0.3 V (VDD being 0 in your case, but the I/O being 3 V). The exact effect of this is unknown, but this is not something I'd recommend you to test.

    Depending on your application, I would consider to leave the nRF51822 continously powered, but just set it in system off when not needed, not actually turn it off. If you do, and have VDD > 2.7 V, you are also allowed to have 3 V on a pin all the time. The chip is supposed to consume < 1 µA in this mode, but due to a PAN, current revisions might consume more. This will be fixed in the upcoming revision.

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