SPIS on nRF51822

[amposlove]

Hello,

While I was making SPIS part, I got several issues.

I am using STM32L151CB for SPI Master and nRF51822 for SPI Slave. It seems many people had issues with SPIS.

SPIS Setting Code is here.

/**************************************************************************************************/

err_code = spi_slave_evt_handler_register(spi_slave_event_handle);
APP_ERROR_CHECK(err_code);    

spi_slave_config.pin_miso      		= SPI1_MISO_PIN;
spi_slave_config.pin_mosi       	= SPI1_MOSI_PIN;
spi_slave_config.pin_sck			= SPI1_SCK_PIN;
spi_slave_config.pin_csn          	= SPI1_CSN_PIN;
spi_slave_config.mode             	= SPI_MODE_1;			// CPOL : 0  / CPHA : 1    From Cortex-M3
spi_slave_config.bit_order        	= SPIM_MSB_FIRST;            
spi_slave_config.def_tx_character	= DEF_CHARACTER;      	// 0xAA
spi_slave_config.orc_tx_character	= ORC_CHARACTER;      	// 0x55

err_code = spi_slave_init(&spi_slave_config);
APP_ERROR_CHECK(err_code);
   
err_code = spi_slave_buffers_set(m_tx_buf, m_rx_buf, sizeof(m_tx_buf), sizeof(m_rx_buf));
APP_ERROR_CHECK(err_code);            

return NRF_SUCCESS;

/**************************************************************************************************/

STM32L151 is using CPOL as 0 and CPHA as 0, so I set SPI_MODE as SPI_MODE_1, and it uses MSB_First.

Is there any problem?

1. Are initial values of MAXRX and MAXTX registers right values?

2. After setting NRF_SPIS1->DEF register, I found something strange on register values.

2.1 NRF_SPIS1->ORC = 0x55 doesn't work at all. See below 2 capture images.

2.2 NRF_SPIS1->SHORTS register is not able to change. See below 2 capture images. Of course, I checked SPIS_SHORTS_END_ACQUIRE_Enabled is 0x01.

3. NRF_SPIS1->INTENCLR is set automatically when NRF_SPIS1->INTENSET is set. See below 2 images.

Because my code can't jump into spi_slave_event_handle(SPIS handler), so I have been struggling with codes, and I want to know whether I made any mistakes for SPIS setting.

Thank you for reading, and I hope to see your answer. Thanks.

Ryan

[Stefan Birnir Sverrisson]

Hi Ryan

• STM32L151 is using CPOL as 0 and CPHA as 0, so I set SPI_MODE as SPI_MODE_1, and it uses MSB_First

Shouldn't you choose the same configuration for the nRF51 SPIS, i.e. SPI_MODE_0?

• Are initial values of MAXRX and MAXTX registers right values?

When you set the buffers in main with spi_slave_buffers_set, a state change is performed with call to

sm_state_change(SPI_BUFFER_RESOURCE_REQUESTED);

that will acquire the semaphore by calling the ACQUIRE task. The application receives in turn the ACQUIRED event where the following code is executed in the SPI1_TWI1_IRQHandler which actually sets the buffer configuration

NRF_SPIS1->TXDPTR = (uint32_t)mp_spi_tx_buf;
NRF_SPIS1->RXDPTR = (uint32_t)mp_spi_rx_buf;
NRF_SPIS1->MAXRX  = m_spi_rx_buf_size;
NRF_SPIS1->MAXTX  = m_spi_tx_buf_size;
            
NRF_SPIS1->TASKS_RELEASE = 1u;
            
sm_state_change(SPI_BUFFER_RESOURCE_CONFIGURED);

• NRF_SPIS1->ORC = 0x55 doesn't work at all. See below 2 capture images.
• NRF_SPIS1->SHORTS register is not able to change. See below 2 capture images. Of course, I checked SPIS_SHORTS_END_ACQUIRE_Enabled is 0x01.

Hmm, that is strange, works fine on my side. Are you sure the value of p_spi_slave_config->orc_tx_character is 0x55? Try to set the compiler optimization level to 0 and disable cache as shown below, clean target and rebuild

• NRF_SPIS1->INTENCLR is set automatically when NRF_SPIS1->INTENSET is set

I can aggree with you, the representation in the debugger is somewhat confusing, but if you disable the interrupts again by writing into the INTENCLR register with the code below then you can see that the interrupt becomes disabled again

• Because my code can't jump into spi_slave_event_handle(SPIS handler)

You should get an SPIS->END event (which will in turn call your spi_slave_event_handle) when the SPI master finishes the transaction by setting CSN high (CSN is active low). Initialize the CSN by letting the SPI master set the CSN to high at the start of your main function. When you want to transmit data, let the SPI master set CSN low, then transmit your data. Then to finish the transaction and get the SPIS->END event, set the CSN high.

What SPI clock frequency have you selected?

Have you tried to run the spi_master_example_with_spi_slave example with the spi_slave_example example, on two boards. Does that work?

[amposlove]

Thank you for your answer.

First of all, I tested with spi_master_example_with_spi_slave example and the spi_slave_example example together, and it doesn't work.

I have 3 RF51822 modules, and every module looks work well on master side, but slave side seems strange include the problems which I report.

Could you check that SPIS->ORC register is changed(I'm sure p_spi_slave_config->orc_tx_character value is 0x55)? Because my code doesn't change the register value, I want check it. I'm using s110_nRF51922_6.0.0 softdevice.

[Stefan Birnir Sverrisson]

What version of nRF51822 do you have, i.e. what are the chip markings on your three nRF51822 chips? Also, are you using softdevice S110 v6.0.0 and nRF51 SDK 5.2.0?

[amposlove]

Package number is marked as N51822QFAAC01319AR, and I'm using softdevice S110 v6.0.0 and nRF51 SDK 5.1.0. Do I need to use SDK 5.2.0?

[Stefan Birnir Sverrisson]

You have the first revision hardware for the nRF51 (QFAAC0), which simply did not have SPI slave present, so that is the reason for your troubles. You should update your hardware to the second revision hardware where the SPIS is present. You can see this in the nRF51 compatibility matrix in nWP_018_v1.3 document found on our web site, in table 1.

nRF51 SDK 5.1.0 is fine with S110 v6.0.0, however nRF51 SDK v5.2.0 is the latest SDK that is compatible with S110 v6.0.0, which includes the most fetures and bugfixes, so it is recommended to use SDK 5.2.0. SDK 5.2.0 however does not include any changes/improvements for SPI/SPIS, so in terms of SPI/SPIS, you should be fine with SDK 5.1.0 (see SDK 5.2.0 release notes).