nRF52 SPI pins incompatibility

[Magners]

Hi, i'm using nRF52 DK to communicate CX93510 encoder chip via SPI. I'm using nrf_drv_spi library with SPI0 connected to pins:

#define CX93510_MISO_PIN 22
#define CX93510_MOSI_PIN 23
#define CX93510_SCK_PIN 24
#define CX93510_CS_PIN 25
#define CX93510_PDRAM_PIN 26
#define CX93510_PD_PIN 27

When my development board with CX93510 not connected to NRF52 DK i can see SPI working correct:

however when i connect CX93510 to my DK board SPI communication ruins - MOSI line dont operate correctly and timings dont match the settings:

I tryied to add 120 Ohm resistors to SPI lines to be sure it is not problem with current flowing through pin - this didnt help. I know that CX93510 chip works good, because i can operate with it with STM8 controller without any problems. Anyone has suggestions how to solve this problem?

[Jørgen Holmefjord]

Hi,

Could you post some code showing how you configure the SPI interface, and how/what you transfer to the device?

Are you able to see data output on the SPI bus if you flash the board with the SPI example from the SDK? Also, which SDK version are you using?

Best regards,
Jørgen

[Jørgen Holmefjord]

Do you have a datasheet for the CX93510 device that you could share? Is the device able to clock out data immediately after the CS line is asserted? From the two logic trances there seems to be some difference in timing. What is the device supposted to clock out? Is 0x00 transferred from the master configuring the device in any way, or does it not need any configuration? 

[Magners]

Yes, it works good. I can see it right now

I guess it is not software problem, but i can't undrstand what exactly wrong with hardware

[Jørgen Holmefjord]

Is the CX93510 chip mounted on some external module or PCB? Is it connected directly to the DK, or is there some other components connected to the SPI lines?

[Magners]

Looks like the problem is the interface selection algorithm of CX93510. It needs SCK line be clocked not later than 3us after CS goes low. Another way it selects UART as host interface

[Jørgen Holmefjord]

Fom your initial images it does not look like any of the devices is clocking the SCK line within 3µs. Is the timing on the images correct, or is does it show wrong resolution? The clock frequency on the second image also looks way lower than 1 MHz that you set in the code. Is the frequency correct?

[Magners]

You are right, increasing frequency to 4 MHz and pulling MISO line to VCC made the diagram much better:

There are still problems with read transaction (last byte), but i think it is out of this topic. 

Thank you for help!