Hi,
I am using ble_app_beacon example and I want to know if DC/DC is enabled by default in the app or should it be enabled like in nrf51 series?
Hi,
I am using ble_app_beacon example and I want to know if DC/DC is enabled by default in the app or should it be enabled like in nrf51 series?
Hi,
The DC/DC is not enabled in the SDK examples. You can enable it using sd_power_dcdc_mode_set().
Hi,
But where do we have to put it before advertising or after that?
Hi,
You can enable the DC/DC at any time after you have enabled the SoftDevice. For example, referring to the SDK 15 BLE examples I would say that it make sense to call sd_power_dcdc_mode_set()
immediately after the call to ble_stack_init().
Hi Einar,
I tried to call sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE); right after the ble_stack_init() but sometimes it makes my application crash. Is it because it's called too soon after the initialization call? When I have the debugger connected the application doesn't crash but without it, it does. It suggests a timing issue.
I had a case where I unknowingly enabled DC/DC, and had the same issue where the program would randomly crash without debugger, but would work fine with debugger attached. In my case it was because I didn't have the necessary external LC filter circuit.
This information explains the last post:
In debug mode only the LDO regulator is enabled (no DCDC, no ULP) and since the LDO is not a switching supply you will get a very stable output voltage in debug mode. After doing a debug reset or pin reset the chip might end up in debug mode (even after disconnecting the debugger), so that probably explains why it looks stable after resetting through SWDebug. After a power cycle, the chip is not in debug mode any longer, and the regulators start to switch.
(Originaly posted by Stian here: https://devzone.nordicsemi.com/f/nordic-q-a/63221/vdd-generated-from-vddh-is-unstable-without-connected-debuger-and-with-non-started-soft-device/266227?focus=true)
This information explains the last post:
In debug mode only the LDO regulator is enabled (no DCDC, no ULP) and since the LDO is not a switching supply you will get a very stable output voltage in debug mode. After doing a debug reset or pin reset the chip might end up in debug mode (even after disconnecting the debugger), so that probably explains why it looks stable after resetting through SWDebug. After a power cycle, the chip is not in debug mode any longer, and the regulators start to switch.
(Originaly posted by Stian here: https://devzone.nordicsemi.com/f/nordic-q-a/63221/vdd-generated-from-vddh-is-unstable-without-connected-debuger-and-with-non-started-soft-device/266227?focus=true)