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NO BSP CALLBACK ON NRF52810

Hi,

I init the bsp for button, but there is no callback in handler when press on button.

The board is NRF52810, and there are so many problems when I test this borad.

It's software is really bad.

These are my code.

#include <string.h>
#include "hal_nfc7963.h"
#include "hal_spi.h"
#include "nordic_common.h"
#include "hal_user.h"
#include "boards.h"
#include "bsp.h"
#include "nrf_log.h"
#include "nrf_log_ctrl.h"
#include "hal_nfc_task.h"
#include "hal_uart.h"
#include "math.h"
#include "app_timer.h"
#include "app_scheduler.h"


#define SCHED_MAX_EVENT_DATA_SIZE       APP_TIMER_SCHED_EVENT_DATA_SIZE             /**< Maximum size of scheduler events. */
#ifdef SVCALL_AS_NORMAL_FUNCTION
#define SCHED_QUEUE_SIZE                20                                          /**< Maximum number of events in the scheduler queue. More is needed in case of Serialization. */
#else
#define SCHED_QUEUE_SIZE                10                                          /**< Maximum number of events in the scheduler queue. */
#endif


uint8_t eve_data = 0;


static void idle_state_handle(void);
static void scheduler_init(void);
static void bsp_evt_handler(bsp_event_t evt);
static void app_sched_event_handle(void * p_event_data, uint16_t event_size);

static void app_sched_event_handle(void * p_event_data, uint16_t event_size)
{
				bsp_board_led_invert(BSP_BOARD_LED_0);
//				hal_beep_enable();
	//			HAL_NFC_SPI_Read(0x00,1);
}
static void bsp_evt_handler(bsp_event_t evt)
{
	switch(evt)
	{
		case BSP_BOARD_BUTTON_0:
			app_sched_event_put(&eve_data,sizeof(eve_data),app_sched_event_handle);

			break;
		default:
			break;
	}
}

void bsp_configuration()
{
    uint32_t err_code;
    err_code = bsp_init(BSP_INIT_BUTTONS | BSP_INIT_LEDS, bsp_evt_handler);
    APP_ERROR_CHECK(err_code);
}

static void scheduler_init(void)
{
    APP_SCHED_INIT(SCHED_MAX_EVENT_DATA_SIZE, SCHED_QUEUE_SIZE);
}


static void idle_state_handle(void)
{
    app_sched_execute();
//    if (NRF_LOG_PROCESS() == false)
//    {
//        nrf_pwr_mgmt_run();
//    }
}


int main(void)
{
	hal_user_init();
//	hal_uart_init();
	bsp_configuration();
//	hal_spi_init();
//	hal_nfc_init();
//	hal_nfc_enable();
	scheduler_init();
	for (;;)
    {
        idle_state_handle();
    }
}

#include <stdbool.h>		
#include "boards.h"
#include "app_error.h"
#include "app_timer.h"
#include "hal_user.h"
#include "app_button.h"
#include "bsp.h"
#include "nrf_drv_clock.h"
#include "sdk_errors.h"
#include "app_error.h"
#include "nrf_log.h"
#include "nrf_log_ctrl.h"
#include "nrf_log_default_backends.h"
#include "nrf_drv_systick.h"
#include "nrf_drv_pwm.h"
#include "app_util_platform.h"
#include "nrf_gpiote.h"
#include "nrf_gpio.h"
#include "nrf_drv_gpiote.h"

static nrf_drv_pwm_t pwm0 = NRF_DRV_PWM_INSTANCE(0);
static uint16_t const              pwm0_top  = 150;
static uint16_t const              pwm0_step = 200;
static nrf_pwm_values_common_t /*const*/ seq_values[] =
    {
             0,
        0x8000,
             0,
        0x8000,
    };
static nrf_pwm_sequence_t const    pwm0_seq =
{
    .values.p_common     = seq_values,
    .length              = NRF_PWM_VALUES_LENGTH(seq_values),
    .repeats             = 0,
    .end_delay           = 0
};

static void pwm_init(void);
static void pwm0_handler(nrf_drv_pwm_evt_type_t event_type);
static void	clock_init(void);
static void timer_init(void);
static void system_clock_init(void);
static void	log_init(void);
static void clock_init(void);
static void drv_clock_init();



static void leds_init(void)
{
    bsp_board_init(BSP_INIT_LEDS);
}


static void pwm0_handler(nrf_drv_pwm_evt_type_t event_type)
{
	if(event_type == NRFX_PWM_EVT_FINISHED || event_type == NRFX_PWM_EVT_STOPPED)
	{
		hal_beep_disable();
	}
}

static void pwm_init()
{
//	nrf_drv_gpiote_out_config_t pwm_pin_config = GPIOTE_CONFIG_OUT_SIMPLE(true);
//	APP_ERROR_CHECK(nrf_drv_gpiote_out_init(BEEP, &pwm_pin_config));

	nrf_drv_pwm_config_t const config0 =
	{
		.output_pins =
		{
			BEEP | NRF_DRV_PWM_PIN_INVERTED, // channel 0
			NRF_DRV_PWM_PIN_NOT_USED,             
            NRF_DRV_PWM_PIN_NOT_USED,              
            NRF_DRV_PWM_PIN_NOT_USED,
		},
		.irq_priority = APP_IRQ_PRIORITY_LOWEST,
		.base_clock   = NRF_PWM_CLK_1MHz,
		.count_mode   = NRF_PWM_MODE_UP,
		.top_value	  = pwm0_top,
		.load_mode	  = NRF_PWM_LOAD_COMMON,
		.step_mode	  = NRF_PWM_STEP_AUTO
	};
	APP_ERROR_CHECK(nrf_drv_pwm_init(&pwm0, &config0, pwm0_handler));
}

void timer_init()
{
	uint32_t err_code;
    err_code = app_timer_init();
    APP_ERROR_CHECK(err_code);
}

static void clock_init()
{
    NRF_CLOCK->LFCLKSRC            = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
    NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
    NRF_CLOCK->TASKS_LFCLKSTART    = 1;

    while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0)
    {
        // Do nothing.
    }

}

static void drv_clock_init()
{
	ret_code_t err_code;
	err_code = nrf_drv_clock_init();
	APP_ERROR_CHECK(err_code);
	nrf_drv_clock_lfclk_request(NULL);
}

static void system_clock_init()
{
	nrf_drv_systick_init();
}

static void log_init()
{
	APP_ERROR_CHECK(NRF_LOG_INIT(NULL));
	NRF_LOG_DEFAULT_BACKENDS_INIT();
}

void hal_user_init()
{
//	hal_user_log_init();
  drv_clock_init();
	clock_init();
	system_clock_init();
	timer_init();
}

void hal_beep_enable()
{
	pwm_init();
	(void)nrf_drv_pwm_simple_playback(&pwm0, &pwm0_seq, 1000, NRFX_PWM_FLAG_STOP);
}

void hal_beep_disable()
{
	nrfx_pwm_stop(&pwm0,false);
	nrfx_pwm_uninit(&pwm0);
	nrfx_gpiote_out_toggle(BEEP);
}

//==========================================================
// <q> BUTTON_ENABLED  - Enables Button module
 

#ifndef BUTTON_ENABLED
#define BUTTON_ENABLED 1
#endif

// <q> BUTTON_HIGH_ACCURACY_ENABLED  - Enables GPIOTE high accuracy for buttons
 

#ifndef BUTTON_HIGH_ACCURACY_ENABLED
#define BUTTON_HIGH_ACCURACY_ENABLED 0
#endif

// <e> APP_TIMER_ENABLED - app_timer - Application timer functionality
//==========================================================
#ifndef APP_TIMER_ENABLED
#define APP_TIMER_ENABLED 1
#endif
// <o> APP_TIMER_CONFIG_RTC_FREQUENCY  - Configure RTC prescaler.
 
// <0=> 32768 Hz 
// <1=> 16384 Hz 
// <3=> 8192 Hz 
// <7=> 4096 Hz 
// <15=> 2048 Hz 
// <31=> 1024 Hz 

#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY
#define APP_TIMER_CONFIG_RTC_FREQUENCY 0
#endif

// <o> APP_TIMER_CONFIG_IRQ_PRIORITY  - Interrupt priority
 

// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
// <0=> 0 (highest) 
// <1=> 1 
// <2=> 2 
// <3=> 3 
// <4=> 4 
// <5=> 5 
// <6=> 6 
// <7=> 7 

#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY
#define APP_TIMER_CONFIG_IRQ_PRIORITY 7
#endif

// <o> APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. 
// <i> Size of the queue depends on how many timers are used
// <i> in the system, how often timers are started and overall
// <i> system latency. If queue size is too small app_timer calls
// <i> will fail.

#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE
#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10
#endif

// <q> APP_TIMER_CONFIG_USE_SCHEDULER  - Enable scheduling app_timer events to app_scheduler
 

#ifndef APP_TIMER_CONFIG_USE_SCHEDULER
#define APP_TIMER_CONFIG_USE_SCHEDULER 0
#endif

// <q> APP_TIMER_KEEPS_RTC_ACTIVE  - Enable RTC always on
 

// <i> If option is enabled RTC is kept running even if there is no active timers.
// <i> This option can be used when app_timer is used for timestamping.

#ifndef APP_TIMER_KEEPS_RTC_ACTIVE
#define APP_TIMER_KEEPS_RTC_ACTIVE 0
#endif

// <h> App Timer Legacy configuration - Legacy configuration.

//==========================================================
// <q> APP_TIMER_WITH_PROFILER  - Enable app_timer profiling
 

#ifndef APP_TIMER_WITH_PROFILER
#define APP_TIMER_WITH_PROFILER 0
#endif

// <q> APP_TIMER_CONFIG_SWI_NUMBER  - Configure SWI instance used.
 

#ifndef APP_TIMER_CONFIG_SWI_NUMBER
#define APP_TIMER_CONFIG_SWI_NUMBER 0
#endif

// </h> 

// <e> RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver - legacy layer
//==========================================================
#ifndef RTC_ENABLED
#define RTC_ENABLED 0
#endif
// <o> RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768> 


#ifndef RTC_DEFAULT_CONFIG_FREQUENCY
#define RTC_DEFAULT_CONFIG_FREQUENCY 32768
#endif

// <q> RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
 

#ifndef RTC_DEFAULT_CONFIG_RELIABLE
#define RTC_DEFAULT_CONFIG_RELIABLE 0
#endif

// <o> RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
 

// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
// <0=> 0 (highest) 
// <1=> 1 
// <2=> 2 
// <3=> 3 
// <4=> 4 
// <5=> 5 
// <6=> 6 
// <7=> 7 

#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY
#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7
#endif

// <q> RTC0_ENABLED  - Enable RTC0 instance
 

#ifndef RTC0_ENABLED
#define RTC0_ENABLED 1
#endif

// <q> RTC1_ENABLED  - Enable RTC1 instance
 

#ifndef RTC1_ENABLED
#define RTC1_ENABLED 1
#endif

// <q> RTC2_ENABLED  - Enable RTC2 instance
 

#ifndef RTC2_ENABLED
#define RTC2_ENABLED 1
#endif
// </e>


// <e> NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver
//==========================================================
#ifndef NRFX_RTC_ENABLED
#define NRFX_RTC_ENABLED 0
#endif
// <q> NRFX_RTC0_ENABLED  - Enable RTC0 instance
 

#ifndef NRFX_RTC0_ENABLED
#define NRFX_RTC0_ENABLED 1
#endif

// <q> NRFX_RTC1_ENABLED  - Enable RTC1 instance
 

#ifndef NRFX_RTC1_ENABLED
#define NRFX_RTC1_ENABLED 1
#endif

// <o> NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt 
#ifndef NRFX_RTC_MAXIMUM_LATENCY_US
#define NRFX_RTC_MAXIMUM_LATENCY_US 2000
#endif

// <o> NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768> 


#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY
#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768
#endif

// <q> NRFX_RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
 

#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE
#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0
#endif

// <o> NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
 
// <0=> 0 (highest) 
// <1=> 1 
// <2=> 2 
// <3=> 3 
// <4=> 4 
// <5=> 5 
// <6=> 6 
// <7=> 7 

#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7
#endif

// <e> NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
//==========================================================
#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
#define NRFX_RTC_CONFIG_LOG_ENABLED 0
#endif
// <o> NRFX_RTC_CONFIG_LOG_LEVEL  - Default Severity level
 
// <0=> Off 
// <1=> Error 
// <2=> Warning 
// <3=> Info 
// <4=> Debug 

#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
#define NRFX_RTC_CONFIG_LOG_LEVEL 3
#endif

// <o> NRFX_RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
 
// <0=> Default 
// <1=> Black 
// <2=> Red 
// <3=> Green 
// <4=> Yellow 
// <5=> Blue 
// <6=> Magenta 
// <7=> Cyan 
// <8=> White 

#ifndef NRFX_RTC_CONFIG_INFO_COLOR
#define NRFX_RTC_CONFIG_INFO_COLOR 0
#endif

// <o> NRFX_RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
 
// <0=> Default 
// <1=> Black 
// <2=> Red 
// <3=> Green 
// <4=> Yellow 
// <5=> Blue 
// <6=> Magenta 
// <7=> Cyan 
// <8=> White 

#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
#define NRFX_RTC_CONFIG_DEBUG_COLOR 0
#endif

// </e>


//==========================================================

//these are my symbol.

BOARD_CUSTOM CONFIG_GPIO_AS_PINRESET DEVELOP_IN_NRF52832 FLOAT_ABI_SOFT NRF52810_XXAA NRF52_PAN_74 __HEAP_SIZE=2048 __STACK_SIZE=2048 USE_APP_CONFIG SWI_DISABLE0

Thanks.

Best Regards.

Parents
  • Hi,

    You have not included any BSP configuration in your sdk_config.h file (the second code snippet in the question). Please refer to an example that use it and copy the BSP configuration to your sdk_config.h file. It seems you are using SDK 15, so you can for example look at the sdk_config.h file for the Heart Rate Application example (<SDK 15>\examples\ble_peripheral\ble_app_hrs\pca10040e\s112\config\sdk_config.h).

  • Hi, 

    I don't use bluetooth, do I add the BSP_BTN_BLE_ENABLED in the sdk_config.h?

    Thanks.

    Best Regards.

  • Hi,

    The BSP_BTN_BLE_ENABLED sdk_config macro enables support for using buttons to do BLE related tasks (delete bonding information, start advertising etc.). There is no reason to enable this if you don't use BLE.

  • Hi,

    I remove the BSP_BTN_BLE_ENABLED related in the sdk_config, it still don't  work. How to solve this 

    problem in NRF52810?

    This file is arm_startup_nrf52810.s, maybe you can get some error information in this file.

    ; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
    ; 
    ;     SPDX-License-Identifier: Apache-2.0
    ; 
    ; Licensed under the Apache License, Version 2.0 (the License); you may
    ; not use this file except in compliance with the License.
    ; You may obtain a copy of the License at
    ; 
    ;     www.apache.org/licenses/LICENSE-2.0
    ; 
    ; Unless required by applicable law or agreed to in writing, software
    ; distributed under the License is distributed on an AS IS BASIS, WITHOUT
    ; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    ; See the License for the specific language governing permissions and
    ; limitations under the License.
    ; 
    ; NOTICE: This file has been modified by Nordic Semiconductor ASA.
    
                    IF :DEF: __STARTUP_CONFIG
    #include "startup_config.h"
    #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
    #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
    #endif
                    ENDIF
    
                    IF :DEF: __STARTUP_CONFIG
    Stack_Size      EQU __STARTUP_CONFIG_STACK_SIZE
                    ELIF :DEF: __STACK_SIZE
    Stack_Size      EQU __STACK_SIZE
                    ELSE
    Stack_Size      EQU     2048
                    ENDIF
                    
                    IF :DEF: __STARTUP_CONFIG
    Stack_Align     EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
                    ELSE
    Stack_Align     EQU 3
                    ENDIF
    
                    AREA    STACK, NOINIT, READWRITE, ALIGN=Stack_Align
    Stack_Mem       SPACE   Stack_Size
    __initial_sp
    
                    IF :DEF: __STARTUP_CONFIG
    Heap_Size       EQU __STARTUP_CONFIG_HEAP_SIZE
                    ELIF :DEF: __HEAP_SIZE
    Heap_Size       EQU __HEAP_SIZE
                    ELSE
    Heap_Size       EQU     2048
                    ENDIF
    
                    AREA    HEAP, NOINIT, READWRITE, ALIGN=3
    __heap_base
    Heap_Mem        SPACE   Heap_Size
    __heap_limit
    
                    PRESERVE8
                    THUMB
    
    ; Vector Table Mapped to Address 0 at Reset
    
                    AREA    RESET, DATA, READONLY
                    EXPORT  __Vectors
                    EXPORT  __Vectors_End
                    EXPORT  __Vectors_Size
    
    __Vectors       DCD     __initial_sp              ; Top of Stack
                    DCD     Reset_Handler
                    DCD     NMI_Handler
                    DCD     HardFault_Handler
                    DCD     MemoryManagement_Handler
                    DCD     BusFault_Handler
                    DCD     UsageFault_Handler
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     SVC_Handler
                    DCD     DebugMon_Handler
                    DCD     0                         ; Reserved
                    DCD     PendSV_Handler
                    DCD     SysTick_Handler
    
                    ; External Interrupts
                    DCD     POWER_CLOCK_IRQHandler
                    DCD     RADIO_IRQHandler
                    DCD     UARTE0_IRQHandler
                    DCD     TWIM0_TWIS0_IRQHandler
                    DCD     SPIM0_SPIS0_IRQHandler
                    DCD     0                         ; Reserved
                    DCD     GPIOTE_IRQHandler
                    DCD     SAADC_IRQHandler
                    DCD     TIMER0_IRQHandler
                    DCD     TIMER1_IRQHandler
                    DCD     TIMER2_IRQHandler
                    DCD     RTC0_IRQHandler
                    DCD     TEMP_IRQHandler
                    DCD     RNG_IRQHandler
                    DCD     ECB_IRQHandler
                    DCD     CCM_AAR_IRQHandler
                    DCD     WDT_IRQHandler
                    DCD     RTC1_IRQHandler
                    DCD     QDEC_IRQHandler
                    DCD     COMP_IRQHandler
                    DCD     SWI0_EGU0_IRQHandler
                    DCD     SWI1_EGU1_IRQHandler
                    DCD     SWI2_IRQHandler
                    DCD     SWI3_IRQHandler
                    DCD     SWI4_IRQHandler
                    DCD     SWI5_IRQHandler
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     PWM0_IRQHandler
                    DCD     PDM_IRQHandler
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
    
    __Vectors_End
    
    __Vectors_Size  EQU     __Vectors_End - __Vectors
    
                    AREA    |.text|, CODE, READONLY
    
    ; Reset Handler
    
    
    Reset_Handler   PROC
                    EXPORT  Reset_Handler             [WEAK]
                    IMPORT  SystemInit
                    IMPORT  __main
    
    
                    LDR     R0, =SystemInit
                    BLX     R0
                    LDR     R0, =__main
                    BX      R0
                    ENDP
    
    ; Dummy Exception Handlers (infinite loops which can be modified)
    
    NMI_Handler     PROC
                    EXPORT  NMI_Handler               [WEAK]
                    B       .
                    ENDP
    HardFault_Handler\
                    PROC
                    EXPORT  HardFault_Handler         [WEAK]
                    B       .
                    ENDP
    MemoryManagement_Handler\
                    PROC
                    EXPORT  MemoryManagement_Handler  [WEAK]
                    B       .
                    ENDP
    BusFault_Handler\
                    PROC
                    EXPORT  BusFault_Handler          [WEAK]
                    B       .
                    ENDP
    UsageFault_Handler\
                    PROC
                    EXPORT  UsageFault_Handler        [WEAK]
                    B       .
                    ENDP
    SVC_Handler     PROC
                    EXPORT  SVC_Handler               [WEAK]
                    B       .
                    ENDP
    DebugMon_Handler\
                    PROC
                    EXPORT  DebugMon_Handler          [WEAK]
                    B       .
                    ENDP
    PendSV_Handler  PROC
                    EXPORT  PendSV_Handler            [WEAK]
                    B       .
                    ENDP
    SysTick_Handler PROC
                    EXPORT  SysTick_Handler           [WEAK]
                    B       .
                    ENDP
    
    Default_Handler PROC
    
                    EXPORT   POWER_CLOCK_IRQHandler [WEAK]
                    EXPORT   RADIO_IRQHandler [WEAK]
                    EXPORT   UARTE0_IRQHandler [WEAK]
                    EXPORT   TWIM0_TWIS0_IRQHandler [WEAK]
                    EXPORT   SPIM0_SPIS0_IRQHandler [WEAK]
                    EXPORT   GPIOTE_IRQHandler [WEAK]
                    EXPORT   SAADC_IRQHandler [WEAK]
                    EXPORT   TIMER0_IRQHandler [WEAK]
                    EXPORT   TIMER1_IRQHandler [WEAK]
                    EXPORT   TIMER2_IRQHandler [WEAK]
                    EXPORT   RTC0_IRQHandler [WEAK]
                    EXPORT   TEMP_IRQHandler [WEAK]
                    EXPORT   RNG_IRQHandler [WEAK]
                    EXPORT   ECB_IRQHandler [WEAK]
                    EXPORT   CCM_AAR_IRQHandler [WEAK]
                    EXPORT   WDT_IRQHandler [WEAK]
                    EXPORT   RTC1_IRQHandler [WEAK]
                    EXPORT   QDEC_IRQHandler [WEAK]
                    EXPORT   COMP_IRQHandler [WEAK]
                    EXPORT   SWI0_EGU0_IRQHandler [WEAK]
                    EXPORT   SWI1_EGU1_IRQHandler [WEAK]
                    EXPORT   SWI2_IRQHandler [WEAK]
                    EXPORT   SWI3_IRQHandler [WEAK]
                    EXPORT   SWI4_IRQHandler [WEAK]
                    EXPORT   SWI5_IRQHandler [WEAK]
                    EXPORT   PWM0_IRQHandler [WEAK]
                    EXPORT   PDM_IRQHandler [WEAK]
    POWER_CLOCK_IRQHandler
    RADIO_IRQHandler
    UARTE0_IRQHandler
    TWIM0_TWIS0_IRQHandler
    SPIM0_SPIS0_IRQHandler
    GPIOTE_IRQHandler
    SAADC_IRQHandler
    TIMER0_IRQHandler
    TIMER1_IRQHandler
    TIMER2_IRQHandler
    RTC0_IRQHandler
    TEMP_IRQHandler
    RNG_IRQHandler
    ECB_IRQHandler
    CCM_AAR_IRQHandler
    WDT_IRQHandler
    RTC1_IRQHandler
    QDEC_IRQHandler
    COMP_IRQHandler
    SWI0_EGU0_IRQHandler
    SWI1_EGU1_IRQHandler
    SWI2_IRQHandler
    SWI3_IRQHandler
    SWI4_IRQHandler
    SWI5_IRQHandler
    PWM0_IRQHandler
    PDM_IRQHandler
                    B .
                    ENDP
                    ALIGN
    
    ; User Initial Stack & Heap
    
                    IF      :DEF:__MICROLIB
    
                    EXPORT  __initial_sp
                    EXPORT  __heap_base
                    EXPORT  __heap_limit
    
                    ELSE
    
                    IMPORT  __use_two_region_memory
                    EXPORT  __user_initial_stackheap
    
    __user_initial_stackheap PROC
    
                    LDR     R0, = Heap_Mem
                    LDR     R1, = (Stack_Mem + Stack_Size)
                    LDR     R2, = (Heap_Mem + Heap_Size)
                    LDR     R3, = Stack_Mem
                    BX      LR
                    ENDP
    
                    ALIGN
    
                    ENDIF
    
                    END
    

    Thanks.

    Best Regards.

Reply
  • Hi,

    I remove the BSP_BTN_BLE_ENABLED related in the sdk_config, it still don't  work. How to solve this 

    problem in NRF52810?

    This file is arm_startup_nrf52810.s, maybe you can get some error information in this file.

    ; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
    ; 
    ;     SPDX-License-Identifier: Apache-2.0
    ; 
    ; Licensed under the Apache License, Version 2.0 (the License); you may
    ; not use this file except in compliance with the License.
    ; You may obtain a copy of the License at
    ; 
    ;     www.apache.org/licenses/LICENSE-2.0
    ; 
    ; Unless required by applicable law or agreed to in writing, software
    ; distributed under the License is distributed on an AS IS BASIS, WITHOUT
    ; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    ; See the License for the specific language governing permissions and
    ; limitations under the License.
    ; 
    ; NOTICE: This file has been modified by Nordic Semiconductor ASA.
    
                    IF :DEF: __STARTUP_CONFIG
    #include "startup_config.h"
    #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
    #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
    #endif
                    ENDIF
    
                    IF :DEF: __STARTUP_CONFIG
    Stack_Size      EQU __STARTUP_CONFIG_STACK_SIZE
                    ELIF :DEF: __STACK_SIZE
    Stack_Size      EQU __STACK_SIZE
                    ELSE
    Stack_Size      EQU     2048
                    ENDIF
                    
                    IF :DEF: __STARTUP_CONFIG
    Stack_Align     EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
                    ELSE
    Stack_Align     EQU 3
                    ENDIF
    
                    AREA    STACK, NOINIT, READWRITE, ALIGN=Stack_Align
    Stack_Mem       SPACE   Stack_Size
    __initial_sp
    
                    IF :DEF: __STARTUP_CONFIG
    Heap_Size       EQU __STARTUP_CONFIG_HEAP_SIZE
                    ELIF :DEF: __HEAP_SIZE
    Heap_Size       EQU __HEAP_SIZE
                    ELSE
    Heap_Size       EQU     2048
                    ENDIF
    
                    AREA    HEAP, NOINIT, READWRITE, ALIGN=3
    __heap_base
    Heap_Mem        SPACE   Heap_Size
    __heap_limit
    
                    PRESERVE8
                    THUMB
    
    ; Vector Table Mapped to Address 0 at Reset
    
                    AREA    RESET, DATA, READONLY
                    EXPORT  __Vectors
                    EXPORT  __Vectors_End
                    EXPORT  __Vectors_Size
    
    __Vectors       DCD     __initial_sp              ; Top of Stack
                    DCD     Reset_Handler
                    DCD     NMI_Handler
                    DCD     HardFault_Handler
                    DCD     MemoryManagement_Handler
                    DCD     BusFault_Handler
                    DCD     UsageFault_Handler
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     SVC_Handler
                    DCD     DebugMon_Handler
                    DCD     0                         ; Reserved
                    DCD     PendSV_Handler
                    DCD     SysTick_Handler
    
                    ; External Interrupts
                    DCD     POWER_CLOCK_IRQHandler
                    DCD     RADIO_IRQHandler
                    DCD     UARTE0_IRQHandler
                    DCD     TWIM0_TWIS0_IRQHandler
                    DCD     SPIM0_SPIS0_IRQHandler
                    DCD     0                         ; Reserved
                    DCD     GPIOTE_IRQHandler
                    DCD     SAADC_IRQHandler
                    DCD     TIMER0_IRQHandler
                    DCD     TIMER1_IRQHandler
                    DCD     TIMER2_IRQHandler
                    DCD     RTC0_IRQHandler
                    DCD     TEMP_IRQHandler
                    DCD     RNG_IRQHandler
                    DCD     ECB_IRQHandler
                    DCD     CCM_AAR_IRQHandler
                    DCD     WDT_IRQHandler
                    DCD     RTC1_IRQHandler
                    DCD     QDEC_IRQHandler
                    DCD     COMP_IRQHandler
                    DCD     SWI0_EGU0_IRQHandler
                    DCD     SWI1_EGU1_IRQHandler
                    DCD     SWI2_IRQHandler
                    DCD     SWI3_IRQHandler
                    DCD     SWI4_IRQHandler
                    DCD     SWI5_IRQHandler
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     PWM0_IRQHandler
                    DCD     PDM_IRQHandler
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
                    DCD     0                         ; Reserved
    
    __Vectors_End
    
    __Vectors_Size  EQU     __Vectors_End - __Vectors
    
                    AREA    |.text|, CODE, READONLY
    
    ; Reset Handler
    
    
    Reset_Handler   PROC
                    EXPORT  Reset_Handler             [WEAK]
                    IMPORT  SystemInit
                    IMPORT  __main
    
    
                    LDR     R0, =SystemInit
                    BLX     R0
                    LDR     R0, =__main
                    BX      R0
                    ENDP
    
    ; Dummy Exception Handlers (infinite loops which can be modified)
    
    NMI_Handler     PROC
                    EXPORT  NMI_Handler               [WEAK]
                    B       .
                    ENDP
    HardFault_Handler\
                    PROC
                    EXPORT  HardFault_Handler         [WEAK]
                    B       .
                    ENDP
    MemoryManagement_Handler\
                    PROC
                    EXPORT  MemoryManagement_Handler  [WEAK]
                    B       .
                    ENDP
    BusFault_Handler\
                    PROC
                    EXPORT  BusFault_Handler          [WEAK]
                    B       .
                    ENDP
    UsageFault_Handler\
                    PROC
                    EXPORT  UsageFault_Handler        [WEAK]
                    B       .
                    ENDP
    SVC_Handler     PROC
                    EXPORT  SVC_Handler               [WEAK]
                    B       .
                    ENDP
    DebugMon_Handler\
                    PROC
                    EXPORT  DebugMon_Handler          [WEAK]
                    B       .
                    ENDP
    PendSV_Handler  PROC
                    EXPORT  PendSV_Handler            [WEAK]
                    B       .
                    ENDP
    SysTick_Handler PROC
                    EXPORT  SysTick_Handler           [WEAK]
                    B       .
                    ENDP
    
    Default_Handler PROC
    
                    EXPORT   POWER_CLOCK_IRQHandler [WEAK]
                    EXPORT   RADIO_IRQHandler [WEAK]
                    EXPORT   UARTE0_IRQHandler [WEAK]
                    EXPORT   TWIM0_TWIS0_IRQHandler [WEAK]
                    EXPORT   SPIM0_SPIS0_IRQHandler [WEAK]
                    EXPORT   GPIOTE_IRQHandler [WEAK]
                    EXPORT   SAADC_IRQHandler [WEAK]
                    EXPORT   TIMER0_IRQHandler [WEAK]
                    EXPORT   TIMER1_IRQHandler [WEAK]
                    EXPORT   TIMER2_IRQHandler [WEAK]
                    EXPORT   RTC0_IRQHandler [WEAK]
                    EXPORT   TEMP_IRQHandler [WEAK]
                    EXPORT   RNG_IRQHandler [WEAK]
                    EXPORT   ECB_IRQHandler [WEAK]
                    EXPORT   CCM_AAR_IRQHandler [WEAK]
                    EXPORT   WDT_IRQHandler [WEAK]
                    EXPORT   RTC1_IRQHandler [WEAK]
                    EXPORT   QDEC_IRQHandler [WEAK]
                    EXPORT   COMP_IRQHandler [WEAK]
                    EXPORT   SWI0_EGU0_IRQHandler [WEAK]
                    EXPORT   SWI1_EGU1_IRQHandler [WEAK]
                    EXPORT   SWI2_IRQHandler [WEAK]
                    EXPORT   SWI3_IRQHandler [WEAK]
                    EXPORT   SWI4_IRQHandler [WEAK]
                    EXPORT   SWI5_IRQHandler [WEAK]
                    EXPORT   PWM0_IRQHandler [WEAK]
                    EXPORT   PDM_IRQHandler [WEAK]
    POWER_CLOCK_IRQHandler
    RADIO_IRQHandler
    UARTE0_IRQHandler
    TWIM0_TWIS0_IRQHandler
    SPIM0_SPIS0_IRQHandler
    GPIOTE_IRQHandler
    SAADC_IRQHandler
    TIMER0_IRQHandler
    TIMER1_IRQHandler
    TIMER2_IRQHandler
    RTC0_IRQHandler
    TEMP_IRQHandler
    RNG_IRQHandler
    ECB_IRQHandler
    CCM_AAR_IRQHandler
    WDT_IRQHandler
    RTC1_IRQHandler
    QDEC_IRQHandler
    COMP_IRQHandler
    SWI0_EGU0_IRQHandler
    SWI1_EGU1_IRQHandler
    SWI2_IRQHandler
    SWI3_IRQHandler
    SWI4_IRQHandler
    SWI5_IRQHandler
    PWM0_IRQHandler
    PDM_IRQHandler
                    B .
                    ENDP
                    ALIGN
    
    ; User Initial Stack & Heap
    
                    IF      :DEF:__MICROLIB
    
                    EXPORT  __initial_sp
                    EXPORT  __heap_base
                    EXPORT  __heap_limit
    
                    ELSE
    
                    IMPORT  __use_two_region_memory
                    EXPORT  __user_initial_stackheap
    
    __user_initial_stackheap PROC
    
                    LDR     R0, = Heap_Mem
                    LDR     R1, = (Stack_Mem + Stack_Size)
                    LDR     R2, = (Heap_Mem + Heap_Size)
                    LDR     R3, = Stack_Mem
                    BX      LR
                    ENDP
    
                    ALIGN
    
                    ENDIF
    
                    END
    

    Thanks.

    Best Regards.

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