Effective impedance of ADC channel in single-shot mode with oversampling in burst mode

[zigenz]

Hi there,

I have suitably designed a battery sampling circuit in my prototype configuration, (Vdd = 1.8V, battery swing = 4.2V to 2.9V) using the app note provided at: https://devzone.nordicsemi.com/b/blog/posts/measuring-lithium-battery-voltage-with-nrf52.  Now that we're revising the design for production, I need to save every joule possible, meaning I need to have the quiescent current through the resistor divider as low as possible.  Current network total resistance is ~6Mohm => ~650nA @ 3.8V nominal.

I found ADC performance a bit flaky in pure single-shot mode (and understandably so), so I have implemented the channel in burst mode with 8x oversampling - it works very nicely.  Sampling is performed at approximately 1 minute intervals.

The app note states that "the sampling frequency should be chosen such that the SAADC input impedance is much larger than the resistor values in the voltage divider", and goes on to state that Rinput = 1 / (fsample * Csample), Csample = 2.5pF.  The app note then assumes a frequency of @ 1 sample per second, to arrive at an effective input impedance of 400Gohm.  It looks like this analysis is performed in pure single-shot mode, once each second, which I feel is neither particularly realistic nor energy efficient.

Assuming I've set my acquisition time to 3us (meaning burst mode can sample at ~5us intervals), the result is a 200kHz sampling frequency - albeit for only 40us.  At 200kHz, the resultant Rinput = 2Mohm, which is < the total network resistance of 6Mohm in my implementation (?!!?!).  To me this suggests that the simplification for estimating Rinput isn't necessarily correct in this case.

I could test various resistor values through trial and error, but I'd prefer a more analytical method.  I was hoping that Nordic could provide some correlation for estimating input impedance assuming that the ADC is used in single-shot burst mode, for a given acquisition time, sample interval, and oversampling rate.

Thanks in advance for the guidance!

-Z

[haakonsh]

The Acquisition time is the time needed to fill the sample and hold capacitor. The larger the source resistance (6Mohm in your case) the longer the acquisition time you'll need to fill the capacitor. See Acquisition time. You should be fine with 40µs acquisition time at > 800kohm. 

I also suggest you sample the battery voltage at peak current in order to determine the actual voltage level of the battery. 

[zigenz]

Thanks haakonsh,

Based on the reference you provided, the MAXIMUM source resistance is 800kohm for a 40us sample time.  I've actually included a 10nF Cext as shown in the second diagram of the app note, meaning I'm largely decoupled from the charging RC characteristic the ADC input (the basis for that table) - Cext will copy its charge straight onto Cinput, making the acquisition time table redundant in this case.

Please refer to the section titled "Choosing the sampling frequency" in the original app note link I provided.  I want to understand how to calculate the effective impedance based on single-shot, burst mode oversampling.

-Z