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best practice - delay between setting pin as input with pull up/pull down and reading the pin

We are seeing a potential issue with a product. on start up a pin is read and the read value determines if we go in to a test mode. Pretty standard. 

Our failure is during normal operation when there is nothing connected to this pin and the firmware is reading a low instead of a high. (On test a test fixture will take the pin to ground)

  1. During normal operation there will be nothing connected to the pin so it is init ally floating floating.
  2. When the firmware starts we set the pin to input and immediately read the value of the pin on the next line

nrf_gpio_cfg_input(TEST_PIN, NRF_GPIO_PIN_PULLUP);
if (!nrf_gpio_pin_read(TEST_PIN)) 
{
	runTestMode();
}

So the question is should I put a delay in between setting the pin as an input with a pull up and reading the pin?

Is it good practice to put a delay in?

(i could of course add an external pull up)

Essentially I will need to look:

  1. The time between the pull up being connected internally to the pin, to when the pin state is read.
  2. the capacitance of the line and the time it takes for the line to go "high" once the pull up has been connected. 

27/7/2018: extra info/questions

Extra marks for considering issues on power up. I.e. assume this code is one of the first things to run.

Nrf51. Pull up values in section 8.23 of the datasheet.

Additional Information:

Please read this post here: https://devzone.nordicsemi.com/f/nordic-q-a/25873/internal-pull-up-resistance-on-gpio-of-nrf51822 

It has a interesting reply on the pull up value with respect the supply voltage on power up. This might depend on how you have the brownout settings configured and when the code is triggered as the voltage rises on power up. equally we may never see this if the code never gets run on supply voltages <1.8V   

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  • Offhand, I believe everything on the gpio is delayed by one pclk. So, the delay depends on how you have pclk configured.

    Yes, it is normal practice to delay a few clocks after setting a register as registers rarely set and latch state on the same clock edge.  Normally I would just throw in a few NOP's after writing the config register depending on the spec for the device.

    The pullup is spec'd as 13kohm so there is no need to worry about the capacitance unless you added one on the pin.

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  • Offhand, I believe everything on the gpio is delayed by one pclk. So, the delay depends on how you have pclk configured.

    Yes, it is normal practice to delay a few clocks after setting a register as registers rarely set and latch state on the same clock edge.  Normally I would just throw in a few NOP's after writing the config register depending on the spec for the device.

    The pullup is spec'd as 13kohm so there is no need to worry about the capacitance unless you added one on the pin.

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