Hi ;
I am using the sdk12.3 spi example to read external flash W25Q16, but it fails . Here is my code. Do you have any suggestion ?
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* Copyright (c) 2015 - 2017, Nordic Semiconductor ASA
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* 1. Redistributions of source code must retain the above copyright notice, this
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
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*/
#include "sdk_common.h"
#include "nrf_drv_spi.h"
#include "nrf_drv_common.h"
#include "nrf_gpio.h"
#include "nrf_assert.h"
#include "app_util_platform.h"
#include "nrf_log.h"
#include "nrf_log_ctrl.h"
#if 0
#define NRF_LOG_MODULE_NAME "SPI"
#if SPI_CONFIG_LOG_ENABLED
#define NRF_LOG_LEVEL SPI_CONFIG_LOG_LEVEL
#define NRF_LOG_INFO_COLOR SPI_CONFIG_INFO_COLOR
#define NRF_LOG_DEBUG_COLOR SPI_CONFIG_DEBUG_COLOR
#else //SPI_CONFIG_LOG_ENABLED
#define NRF_LOG_LEVEL 0
#endif //SPI_CONFIG_LOG_ENABLED
#include "nrf_log.h"
#endif
#define IRQ_HANDLER(n) void SPI##n##_IRQ_HANDLER(void)
/* Defines -------------------------------------------------------------------*/
/* Flash ID */
#define GD25Q32_FLASH_ID 0xC8
/* Status Register Bits */
#define STATUS_BUSY 0x01
#define STATUS_WEL 0x02
#define STATUS_BP0 0x04
#define STATUS_BP1 0x08
#define STATUS_TB 0x20
#define STATUS_SRP 0x80
/* Flash operation command */
#define WRITE_STATUS_REG 0x01
#define PAGE_PROGRAM 0x02
#define READ_DATA_BYTE 0x03
#define READ_STATUS_REG 0x05
#define CHIP_EARSE 0x60
#define READ_ID 0x9f
/** @addtogroup Exported_types
* @{
*/
// Control block - driver instance local data.
typedef struct
{
nrf_drv_spi_handler_t handler;
nrf_drv_spi_evt_t evt; // Keep the struct that is ready for event handler. Less memcpy.
nrf_drv_state_t state;
volatile bool transfer_in_progress;
// [no need for 'volatile' attribute for the following members, as they
// are not concurrently used in IRQ handlers and main line code]
uint8_t ss_pin;
uint8_t orc;
uint8_t bytes_transferred;
bool tx_done : 1;
bool rx_done : 1;
} spi_control_block_t;
static spi_control_block_t m_cb[1];
/*******************************************************************************************/
//static volatile bool spi_xfer_done; /**< Flag used to indicate that SPI instance completed the transfer. */
extern bool spi_xfer_done;
/**
* @brief SPI user event handler.
* @param event
*/
void spi_event_handler(nrf_drv_spi_evt_t const * p_event)
{
spi_xfer_done = true;
NRF_LOG_INFO("Transfer completed.\r\n");
// if (m_rx_buf[0] != 0)
{
NRF_LOG_INFO(" Received: \r\n");
// NRF_LOG_HEXDUMP_INFO(m_rx_buf, strlen((const char *)m_rx_buf));
}
}
ret_code_t nrf_drv_spi_init(nrf_drv_spi_t const * const p_instance,
nrf_drv_spi_config_t const * p_config,
nrf_drv_spi_handler_t handler)
{
ASSERT(p_config);
spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
ret_code_t err_code;
p_cb->handler = handler;
uint32_t mosi_pin;
uint32_t miso_pin;
// Configure pins used by the peripheral:
// - SCK - output with initial value corresponding with the SPI mode used:
// 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1);
// according to the reference manual guidelines this pin and its input
// buffer must always be connected for the SPI to work.
if (p_config->mode <= NRF_DRV_SPI_MODE_1)
{
nrf_gpio_pin_clear(p_config->sck_pin);
}
else
{
nrf_gpio_pin_set(p_config->sck_pin);
}
NRF_GPIO->PIN_CNF[p_config->sck_pin] =
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos);
// - MOSI (optional) - output with initial value 0,
mosi_pin = p_config->mosi_pin;
nrf_gpio_pin_clear(mosi_pin);
nrf_gpio_cfg_output(mosi_pin);
// - MISO (optional) - input,
miso_pin = p_config->miso_pin;
nrf_gpio_cfg_input(miso_pin, NRF_GPIO_PIN_NOPULL);
// - Slave Select (optional) - output with initial value 1 (inactive).
nrf_gpio_pin_set(p_config->ss_pin);
nrf_gpio_cfg_output(p_config->ss_pin);
m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin;
NRF_SPI_Type * p_spi = p_instance->p_registers;
nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin);
nrf_spi_frequency_set(p_spi,
(nrf_spi_frequency_t)p_config->frequency);
nrf_spi_configure(p_spi,
(nrf_spi_mode_t)p_config->mode,
(nrf_spi_bit_order_t)p_config->bit_order);
m_cb[p_instance->drv_inst_idx].orc = p_config->orc;
if (p_cb->handler)
{
nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK);
}
nrf_spi_enable(p_spi);
if (p_cb->handler)
{
nrf_drv_common_irq_enable(p_instance->irq, p_config->irq_priority);
}
p_cb->transfer_in_progress = false;
p_cb->state = NRF_DRV_STATE_INITIALIZED;
NRF_LOG_INFO("Init\r\n");
err_code = NRF_SUCCESS;
NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
return err_code;
}
void nrf_drv_spi_uninit(nrf_drv_spi_t const * const p_instance)
{
spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
if (p_cb->handler)
{
nrf_drv_common_irq_disable(p_instance->irq);
}
#define DISABLE_ALL 0xFFFFFFFF
NRF_SPI_Type * p_spi = p_instance->p_registers;
if (p_cb->handler)
{
nrf_spi_int_disable(p_spi, DISABLE_ALL);
}
nrf_spi_disable(p_spi);
#undef DISABLE_ALL
p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
}
ret_code_t nrf_drv_spi_transfer(nrf_drv_spi_t const * const p_instance,
uint8_t * p_tx_buffer,
uint8_t tx_buffer_length,
uint8_t * p_rx_buffer,
uint8_t rx_buffer_length)
{
nrf_drv_spi_xfer_desc_t xfer_desc;
NRF_SPI_Type * p_spi = p_instance->p_registers;
nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
xfer_desc.p_tx_buffer = p_tx_buffer;
xfer_desc.tx_length = tx_buffer_length;
xfer_desc.p_rx_buffer = p_rx_buffer;
xfer_desc.rx_length = rx_buffer_length;
NRF_LOG_DEBUG("Tx data:\r\n");
NRF_LOG_DEBUG("%x\r\n",p_tx_buffer[0] );
NRF_LOG_INFO("Transfer tx_len:%d, rx_len:%d.\r\n", tx_buffer_length, rx_buffer_length);
NRF_LOG_FLUSH();
return nrf_drv_spi_xfer(p_instance, &xfer_desc, 0);
}
static void finish_transfer(spi_control_block_t * p_cb)
{
// If Slave Select signal is used, this is the time to deactivate it.
if (p_cb->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
{
nrf_gpio_pin_set(p_cb->ss_pin);
}
// By clearing this flag before calling the handler we allow subsequent
// transfers to be started directly from the handler function.
p_cb->transfer_in_progress = false;
p_cb->evt.type = NRF_DRV_SPI_EVENT_DONE;
NRF_LOG_INFO("finish_transfer rx_len:%d.\r\n", p_cb->evt.data.done.rx_length);
NRF_LOG_DEBUG("Rx data:\r\n");
NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_cb->evt.data.done.p_rx_buffer,
p_cb->evt.data.done.rx_length * sizeof(p_cb->evt.data.done.p_rx_buffer));
p_cb->handler(&p_cb->evt);
}
// This function is called from IRQ handler or, in blocking mode, directly
// from the 'nrf_drv_spi_transfer' function.
// It returns true as long as the transfer should be continued, otherwise (when
// there is nothing more to send/receive) it returns false.
static bool transfer_byte(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb)
{
// Read the data byte received in this transfer and store it in RX buffer,
// if needed.
volatile uint8_t rx_data = nrf_spi_rxd_get(p_spi);
if (p_cb->bytes_transferred < p_cb->evt.data.done.rx_length)
{
if(READ_DATA_BYTE == p_cb->evt.data.done.p_tx_buffer[0])
{
if(p_cb->bytes_transferred >= 4)
{
p_cb->evt.data.done.p_rx_buffer[p_cb->bytes_transferred-4] = rx_data;
}
}
else
{
p_cb->evt.data.done.p_rx_buffer[p_cb->bytes_transferred] = rx_data;
}
}
++p_cb->bytes_transferred;
// Check if there are more bytes to send or receive and write proper data
// byte (next one from TX buffer or over-run character) to the TXD register
// when needed.
// NOTE - we've already used 'p_cb->bytes_transferred + 1' bytes from our
// buffers, because we take advantage of double buffering of TXD
// register (so in effect one byte is still being transmitted now);
// see how the transfer is started in the 'nrf_drv_spi_transfer'
// function.
// uint16_t bytes_used = p_cb->bytes_transferred + 1;
// if (bytes_used < p_cb->evt.data.done.tx_length)
if (p_cb->bytes_transferred < p_cb->evt.data.done.tx_length)
{
// NRF_LOG_DEBUG("transfer_byte Tx0 data:%x\r\n", p_cb->evt.data.done.p_tx_buffer[bytes_used]);
// nrf_spi_txd_set(p_spi, p_cb->evt.data.done.p_tx_buffer[bytes_used]);
// NRF_LOG_DEBUG("transfer_byte Tx0 data:%x\r\n", p_cb->evt.data.done.p_tx_buffer[p_cb->bytes_transferred]);
nrf_spi_txd_set(p_spi, p_cb->evt.data.done.p_tx_buffer[p_cb->bytes_transferred]);
return true;
}
//else if (bytes_used < p_cb->evt.data.done.rx_length)
else if (p_cb->bytes_transferred < p_cb->evt.data.done.rx_length)
{
// NRF_LOG_DEBUG("transfer_byte Tx1 data:%x\r\n", p_cb->orc);
nrf_spi_txd_set(p_spi, p_cb->orc);
return true;
}
return (p_cb->bytes_transferred < p_cb->evt.data.done.tx_length ||
p_cb->bytes_transferred < p_cb->evt.data.done.rx_length);
}
static void spi_xfer(NRF_SPI_Type * p_spi,
spi_control_block_t * p_cb,
nrf_drv_spi_xfer_desc_t const * p_xfer_desc)
{
p_cb->bytes_transferred = 0;
nrf_spi_int_disable(p_spi, NRF_SPI_INT_READY_MASK);
nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
nrf_spi_txd_set(p_spi, p_xfer_desc->tx_length > 0 ? p_xfer_desc->p_tx_buffer[0] : p_cb->orc);
// TXD register is double buffered, so next byte to be transmitted can
// be written immediately, if needed, i.e. if TX or RX transfer is to
// be more that 1 byte long. Again - if there is something more in TX
// buffer send it, otherwise use over-run character.
#if 0
if (p_xfer_desc->tx_length > 1)
{
nrf_spi_txd_set(p_spi, p_xfer_desc->p_tx_buffer[1]);
}
else if (p_xfer_desc->rx_length > 1)
{
nrf_spi_txd_set(p_spi, p_cb->orc);
}
#endif
// For blocking mode (user handler not provided) wait here for READY
// events (indicating that the byte from TXD register was transmitted
// and a new incoming byte was moved to the RXD register) and continue
// transaction until all requested bytes are transferred.
// In non-blocking mode - IRQ service routine will do this stuff.
if (p_cb->handler)
{
nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK);
}
else
{
do {
while (!nrf_spi_event_check(p_spi, NRF_SPI_EVENT_READY)) {}
nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
NRF_LOG_DEBUG("SPI: Event: NRF_SPI_EVENT_READY.\r\n");
} while (transfer_byte(p_spi, p_cb));
if (p_cb->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
{
nrf_gpio_pin_set(p_cb->ss_pin);
}
}
}
ret_code_t nrf_drv_spi_xfer(nrf_drv_spi_t const * const p_instance,
nrf_drv_spi_xfer_desc_t const * p_xfer_desc,
uint32_t flags)
{
spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0);
// ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0);
ret_code_t err_code = NRF_SUCCESS;
if (p_cb->transfer_in_progress)
{
err_code = NRF_ERROR_BUSY;
NRF_LOG_WARNING("nrf_drv_spi_xfer Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
return err_code;
}
else
{
if (p_cb->handler && !(flags & (NRF_DRV_SPI_FLAG_REPEATED_XFER | NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER)))
{
p_cb->transfer_in_progress = true;
}
}
p_cb->evt.data.done = *p_xfer_desc;
p_cb->tx_done = false;
p_cb->rx_done = false;
nrf_gpio_pin_clear(p_cb->ss_pin);
if (flags)
{
p_cb->transfer_in_progress = false;
err_code = NRF_ERROR_NOT_SUPPORTED;
}
else
{
spi_xfer(p_instance->p_registers, p_cb, p_xfer_desc);
}
NRF_LOG_INFO("nrf_drv_spi_xfer_1 Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
return err_code;
}
/**
* @brief Read status register of flash.
* @param none.
* @return value of status register.
*
*/
uint8_t ExternalFlash_ReadStatus(nrf_drv_spi_t const * const p_instance)
{
uint8_t sendBuf[2] = {READ_STATUS_REG, 0}; // 05 read register
uint8_t irecvBuf[2], recv_len = 2;;
spi_xfer_done = false;
APP_ERROR_CHECK(nrf_drv_spi_transfer(p_instance, sendBuf, sizeof(sendBuf), irecvBuf, recv_len));
while (!spi_xfer_done)
{
__WFE();
}
return irecvBuf[1];
}
/**
* @brief Check flash is in progress or not.
* @param none.
* @return SET: Flash is always in progress. RESET: Flash is in standby mode.
*
*/
FlagStatus ExternalFlash_CheckWriteStatus(nrf_drv_spi_t const * const p_instance)
{
uint32_t time_out = 0xfffff;
uint8_t status = 0;
do
{
/* Time out control */
time_out--;
if(time_out == 0)
{
return SET;
}
status = ExternalFlash_ReadStatus(p_instance);
}
while(status & STATUS_BUSY);/* Check flash is communicating or not */
return RESET;
}
/**
* @brief Send write enable command before every page program(PP),
* sector earse(SE), block earse(BE), chip earse(CE) and write status register(WRSR) command.
* @param No parameter.
* @return void
*
*/
void ExternalFlash_WriteCmd(nrf_drv_spi_t const * const p_instance, FunctionalState NewState)
{
uint8_t cmd, send_len = 1;
uint8_t recvBuf[1], recv_len = 1;
/* Check earse status */
ExternalFlash_CheckWriteStatus(p_instance);
/* Send write command */
if(NewState == ENABLE)
{
/* Send write enable command */
cmd = 0x06;
}
else
{
/* Send write disable command */
cmd = 0x04;
}
spi_xfer_done = false;
APP_ERROR_CHECK(nrf_drv_spi_transfer(p_instance, &cmd, send_len, recvBuf, recv_len));
while (!spi_xfer_done)
{
__WFE();
}
/* Check earse status */
ExternalFlash_CheckWriteStatus(p_instance);
}
/**
* @brief Earse flash.
* @param address: address which begin to earse.
* @param mode: select earse mode.
* @return none.
*
*/
void ExternalFlash_Earse(nrf_drv_spi_t const * const p_instance,uint32_t address, Flash_erase_module_t mode)
{
uint8_t sendBuf[4],recvBuf[4];
uint8_t send_len = 4;
uint16_t recv_len = 4;
/* Enable write */
ExternalFlash_WriteCmd(p_instance,ENABLE);
/* Write data */
sendBuf[0] = mode;
sendBuf[1] = (address>>16) & 0xff;
sendBuf[2] = (address>>8) & 0xff;
sendBuf[3] = address & 0xff;
spi_xfer_done = false;
APP_ERROR_CHECK(nrf_drv_spi_transfer(p_instance, sendBuf, send_len, recvBuf, recv_len));
while (!spi_xfer_done)
{
__WFE();
}
APP_ERROR_CHECK(nrf_drv_spi_transfer(p_instance, sendBuf, send_len, recvBuf, recv_len));
}
/**
* @brief Write flash.
* @param address: address which begin to write.
* @param psendBuf: address of data buffer which want to write.
* @param len: length of data buffer which want to write.
* @return none.
*
*/
void ExternalFlash_Write(nrf_drv_spi_t const * const p_instance,uint32_t address, uint8_t *psendBuf, uint16_t len)
{
uint8_t sendBuf[255], recvBuf[1];// = {PAGE_PROGRAM, 0, 0, 0},recvBuf[10];
/* Enable write */
ExternalFlash_WriteCmd(p_instance,ENABLE);
/* Send write command */
sendBuf[0] = 0x02;
sendBuf[1] = (address>>16) & 0xff;
sendBuf[2] = (address>>8) & 0xff;
sendBuf[3] = address & 0xff;
/* Send write data */
memcpy(&sendBuf[4], psendBuf, len);
len = len + 4;
spi_xfer_done = false;
nrf_drv_spi_transfer(p_instance, sendBuf, len, recvBuf,0);//recvBuf, 30);
while (!spi_xfer_done)
{
__WFE();
}
}
/**
* @brief Read flash.
* @param address: address which begin to read.
* @param pStoreBuf: address of data buffer which want to read.
* @param len: length of data buffer which want to read.
* @return none.
*
*/
void ExternalFlash_Read(nrf_drv_spi_t const * const p_instance,uint32_t address, uint8_t *pStoreBuf, uint16_t len)
{
uint8_t sendBuf[4] ={READ_DATA_BYTE,0,0,0};
/* Read flash status register */
ExternalFlash_CheckWriteStatus(p_instance);
/* Send read command and address */
sendBuf[0] = READ_DATA_BYTE;
sendBuf[1] = (address>>16) & 0xff;
sendBuf[2] = (address>>8) & 0xff;
sendBuf[3] = address & 0xff;
spi_xfer_done = false;
APP_ERROR_CHECK(nrf_drv_spi_transfer(p_instance, sendBuf, 4, pStoreBuf, len));
while (!spi_xfer_done)
{
__WFE();
}
}
static void irq_handler_spi(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb)
{
ASSERT(p_cb->handler);
nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
if (!transfer_byte(p_spi, p_cb))
{
finish_transfer(p_cb);
}
}
#if NRF_MODULE_ENABLED(SPI0)
IRQ_HANDLER(0)
{
spi_control_block_t * p_cb = &m_cb[SPI0_INSTANCE_INDEX];
#if SPI0_USE_EASY_DMA
irq_handler_spim(NRF_SPIM0, p_cb);
#else
irq_handler_spi(NRF_SPI0, p_cb);
#endif
}
#endif // NRF_MODULE_ENABLED(SPI0)
#if NRF_MODULE_ENABLED(SPI1)
IRQ_HANDLER(1)
{
spi_control_block_t * p_cb = &m_cb[SPI1_INSTANCE_INDEX];
#if SPI1_USE_EASY_DMA
irq_handler_spim(NRF_SPIM1, p_cb);
#else
irq_handler_spi(NRF_SPI1, p_cb);
#endif
}
#endif // NRF_MODULE_ENABLED(SPI1)
#if NRF_MODULE_ENABLED(SPI2)
IRQ_HANDLER(2)
{
spi_control_block_t * p_cb = &m_cb[SPI2_INSTANCE_INDEX];
#if SPI2_USE_EASY_DMA
irq_handler_spim(NRF_SPIM2, p_cb);
#else
irq_handler_spi(NRF_SPI2, p_cb);
#endif
}
#endif // NRF_MODULE_ENABLED(SPI2)
