nrf52832 spi (PSEL.SCK)

[yanli_1226]

I use nrf52832 SPIM, and I want there are gaps between every 8clock, so I set  NRF_SPIM0->TXD.MAXCNT = 1; NRF_SPIM0->RXD.MAXCNT = 1; ,But there is alway more clock than I want,(I want to write 8clock, but there are 16clock), then the nordic engineer tell me to use PPI(setup_workaround_for_ftpan_58). now, the SPI work well , but I find another question, I must put P0.30 as output pin,and there is gaps between every 8clock, If I didn't config P0.30, there is not gaps between every 8clock, just like bellow,is that right?

I asked the quetion in https://devzone.nordicsemi.com/f/nordic-q-a/40522/nrf52832-spi-psel-sck-timing, but there is no reply.There are more details in the link.

[Jared]

Hi,

I'm not sure i understand your problem.

• What do you mean by output pin? The data pin for SPI? A GPIO pin? 
• What is shown in the picture? The clock signal? The data line?
• What is meant by not configuring P0.30?

Best regards

Jared 

[yanli_1226]

the picture is SPI SCK, I want the SPI SCK to have gaps between every 8 clock, so I use NRF_SPIM0->TXD.MAXCNT = 1; NRF_SPIM0->RXD.MAXCNT = 1; 

P0.30 is an IO, not used as an SPI pin, but I find that , if I not config P0.30 as a output pin, there are not gaps between every 8 clock, just like the picture shows. IF I config P0.30 as a output pin(I config P0.30 like this:nrf_gpio_cfg_output(30); nrf_gpio_pin_clear(30);), there are gaps between every 8 clock just as what I want. 

the question is :P0.30 is not used as an SPI pin, why it influences the SPI SCK Waveform。the SPI code is just like bellow:

[Jared]

I find this very strange. Could you share your code so I could try to reproduce the error? 

[yanli_1226]

Thanks, the code is just as bellow:

nrf52832_SPI_VTEST.rar

In main.c , if I comment the following, there are not gaps between every 8 SPI SCK 

//nrf_gpio_cfg_output(30);    // if pin30 is not set output and set1/clear0,spi sck is not right
//nrf_gpio_pin_clear(30);
//last_valid_cmd[0] = 0;

If I not comment the following,there are gaps between every 8 SPI SCK 

nrf_gpio_cfg_output(30); // if pin30 is not set output and set1/clear0,spi sck is not right
nrf_gpio_pin_clear(30);
last_valid_cmd[0] = 0;

that's strange, I don't know what's the matter?

[Jared]

It doesn't seem that it is the initialization of the GPIO that is causing the issue but rather the initialization of the last_valid_cmd[0] = 0. Which SDK are you using?

[yanli_1226]

I use the example installed in keil/ARM/pack

[Jared]

I meant to write: Which SDK Version are you using? Have you tried commenting out the line last_valid_cmd[0] = 0 and see if the issue persists?

[yanli_1226]

how to get SDK version，I download the example from ARM/pack

[yanli_1226]

config like this:

spi_master_init();
nrf_gpio_cfg_output(30); // if pin30 is not set output and set1/clear0,spi sck is not right
nrf_gpio_pin_clear(30);
//last_valid_cmd[0] = 0;

or config like this:

spi_master_init();
//nrf_gpio_cfg_output(30); // if pin30 is not set output and set1/clear0,spi sck is not right
//nrf_gpio_pin_clear(30);
last_valid_cmd[0] = 0;

there are not gaps between every 8clocks, only config like this:

spi_master_init();
nrf_gpio_cfg_output(30); // if pin30 is not set output and set1/clear0,spi sck is not right
nrf_gpio_pin_clear(30);
last_valid_cmd[0] = 0;

there are  gaps between every 8clocks