OK - so I just started with these chips, and have been asked to find out why SWO debug signal is getting corrupted.
At fairly random intervals the signal passive state inverts from 0 to 1, which corrupts the next few lines of debug output until the passive state inverts back again.
I suspect a silicon bug, or a conflict between something like GPIO and the ITM, but wanted to start by double-checking the hardware configuration settings.
The SWO is configured as follows, but there are quite a few magic numbers in there.
// brief Initialize the SWO trace port for debug message printing
// param portBits Port bit mask to be configured
void SWO_Init(uint32_t portBits)
uint32_t SWOSpeed = 57600; // baud rate
uint32_t SWOPrescaler = (CPU_CORE_FREQUENCY_HZ / SWOSpeed) + 1; // SWOSpeed in Hz, note that CPU_CORE_FREQUENCY_HZ is expected to be match the CPU core clock
CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk; // enable trace in core debug */
*((volatile unsigned *)(ITM_BASE + 0x400F0)) = 0x00000002; // "Selected PIN Protocol Register": Select which protocol to use for trace output (2: SWO NRZ, 1: SWO Manchester encoding)
*((volatile unsigned *)(ITM_BASE + 0x40010)) = SWOPrescaler; // "Async Clock Prescaler Register". Scale the baud rate of the asynchronous output
*((volatile unsigned *)(ITM_BASE + 0x00FB0)) = 0xC5ACCE55; // ITM Lock Access Register, C5ACCE55 enables more write access to Control Register 0xE00 :: 0xFFC
ITM->TCR = ITM_TCR_TraceBusID_Msk | ITM_TCR_SWOENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_ITMENA_Msk; // ITM Trace Control Register
ITM->TPR = ITM_TPR_PRIVMASK_Msk; // ITM Trace Privilege Register
ITM->TER = portBits; // ITM Trace Enable Register. Enabled tracing on stimulus ports. One bit per stimulus port.
*((volatile unsigned *)(ITM_BASE + 0x01000)) = 0x400003FE; // DWT_CTRL
*((volatile unsigned *)(ITM_BASE + 0x40304)) = 0x00000100; // Formatter and Flush Control Register
So first question - anybody know where I can find the register definitions?
I followed this thread about SWO but it took me to the Infocenter, which has been deprecated and I cannot find a reference manual for the 52832
Thanks in advance
Yes, we had some problems with the Doclib's nRF52832 section. But all HW related information on infocenter is still the same, so that part isn't really outdated.
I haven't tested your implementation, but I did try the one you linked to (this one) a couple of times earlier, and that worked. Do you get the same error with that implementation?
Where do you measure that the bit is flipping? Do you measure the pin from the nRF, or from the On Board (OB) Segger chip?
Thanks for the prompt response.
I am picking up on a GCC project which is in pre-production, so don't want to muck about with the code until I am sure. Not sure if this debugging software came from an appnote/example, or if it was invented locally.
The link from that previous thread throws a 404 error here . If the documentation exists, can you give me a pointer to the reference manual with register definitions for ITM please?
The bit flip appears on the pin of the Laird BL652 SA01, I don't think that has segger OB.
Also, I noticed that the implementation uses
Oh. Sorry. I didn't test the link. From the link address, it looks like it is here:
I have not tested, but it looks like the SWO pin, if you use serial, and not parallel, is P0.18. Is that the one you are using?
Are you sure SWO is what you really are looking at using? It is typically a debugging tool (If you have a debugger that is connected to that pin).
Maybe what you really want to is to enable logging? UART?
I am finding some of the information for the ITM in the ARM infocenter.
the section on the ITM states this..."Other registers are described in the ARM®v7-M Architectural Reference Manual."
And that document is "only available to registered ARM customers"...
Which perhaps explains why I cannot find out what the code is supposed to do. :roll:
Yes - the project uses pin 18 as SWO. it is used for runtime logging, and there is no room on board for a uart connection.
Also, I found a CMSIS function ITM_Sendchar in core_cm4.h that does 8-bit writes to ITM->PORT.u8 , so I am less worried about that now.