nRF52840 SPI setup/hold timing issue related to AMOLED driver IC

[ChaceC]

 Please kindly help to push this emergent issue!!!

     

   We detected CLK signal using oscilloscope as picture below:

  

   We can see that clock frequency is set to 32MHz,but we detected the rise time is nearly 4.2ns, from the AMOLED specification, rise/fall time has to be limited under 2ns, otherwise, it will leads to unpredictable read or write faulty issue 。

  

   Feedback from AMOLED vendor shows that clock rise time and fall time must be within the specification(less than 2ns), 

   Moreover,we probed the setup/hold timing for CLK and MOSI, as below.

   It is not equal for setup time and hold time,setup time is much less than hold time

   

My question as below:

   1. Please help to confirm if there is a solution for this issue to reduce the rise/fall time，which means a big issue for our product design

 

   2. Is there some solution to change the timing charcteristic for CLK and MOSI from MCU firmware,?It will be much better if setup time can match with hold time,which is highly recommended by AMOLED vendor.

   Looking forward to your reply A.S.A.P.

[haakonsh]

1. Try setting the GPIO drive strength of your pins to high. See nrf_gpio_cfg, nrf_gpio_pin_drive_t, and NRF_GPIO_PIN_H0H1. 
   
   How have you connected the devices, I ask because the CLK signal seems to be quite capacitively loaded. The GPIO pin and pad has about 4pF capacitance and a standard oscilloscope probe has about 12pF, what other sources of capacitance do you have?
   
   If you have access to an active oscilloscope probe I suggest you used that as it will not load the I/O lines. 
   
   
2. No I'm afraid not. From Timing specifications the setup and hold times are almost identical already, It's the capacitive loading that ruins the operation here.