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Several problems with the qspi library function

Hi,Master:

1.The timing of the underlying  nrfx_qspi_write(...)  function is:a. Send 05 to check if the wip bit is 0. (Here, if wip is not 0, will it always detect until wip is 0?)

2. Is the register ADDRCONF  used for what purpose?

3.the nrfx_qspi_init(...) function will trigger the status register timing, and the task is activated(As shown below). How does the peripheral determine that it is activated successfully? What does this function do internally to the underlying layer? 

nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_ACTIVATE);

// Waiting for the peripheral to activate
bool result;
NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY),
QSPI_DEF_WAIT_ATTEMPTS,
QSPI_DEF_WAIT_TIME_US,
result);

4.Is there a bug in the nrf_qspi_cinstrdata_get(...) function? When the length is greater than NRF_QSPI_CINSTR_LEN_5B, the data of <= NRF_QSPI_CINSTR_LEN_5B cannot be obtained.So I added the code for the red area

Thanks!

Parents
  • Hi

    1.

    .The timing of the underlying  nrfx_qspi_write(...)  function is:a

    Sorry, I'm struggling to understand what you mean by this. Could you please clarify?

    2. The ADDRCONF register is used for extended address configuration in the QSPI, controlling the use of extended 32-bit addressing with optional data bytes following the Opcode that puts the device into the 32-bit addressing mode.

    3. Triggering this task activates the external flash memory interface and initiates communication with the external memory. The READY event is generated when the activation has been completed.

    4. Yes, this is a bug (mentioned in this post).

     Best regards,

    Simon

Reply
  • Hi

    1.

    .The timing of the underlying  nrfx_qspi_write(...)  function is:a

    Sorry, I'm struggling to understand what you mean by this. Could you please clarify?

    2. The ADDRCONF register is used for extended address configuration in the QSPI, controlling the use of extended 32-bit addressing with optional data bytes following the Opcode that puts the device into the 32-bit addressing mode.

    3. Triggering this task activates the external flash memory interface and initiates communication with the external memory. The READY event is generated when the activation has been completed.

    4. Yes, this is a bug (mentioned in this post).

     Best regards,

    Simon

Children
  • Hi,Simon

    Thank you for your answer, you have helped me solve the 2 and 4 questions, thank you.

    1.Nrfx_qspi_write(...) The underlying oscilloscope observes the timing. It will send 0x05 to confirm whether the status register wip bit is 0. If it is not 0, will it always query until it is 0? In this case, I don't need to add code to check the wip bit when calling this function.

    2.I also want to ask you another question.When I use the QSPI library to communicate with flash, first initialize nrfx_qspi_init(&config, NULL, NULL) (handler parameter is NULL, ie: qspi internal interrupt is not enabled); after reading and writing, call nrfx_qspi_uninit() to reduce power consumption , but there will always be qspi interrupt hangs in NVIC, which will result in main

    for(;;)

    {

    App_sched_execute();

    Ble_idle_state();

    Sys_wdt_feed();

    }

    is always woken up, resulting in an average power consumption that cannot be reduced. This problem can be solved by adding NRFX_IRQ_PENDING_CLEAR(QSPI_IRQn) after calling nrfx_qspi_uninit(). why? Is there any hidden problem that needs attention in other places on the nordic platform? Thank you

     Best regards

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