nRF52832: Pin state _during_ reset (Retained registers)

[Tobias Schneider]

Hi,

in https://devzone.nordicsemi.com/f/nordic-q-a/24115/io-pin-signal-during-reset it is mentioned that the pins of the nRF52832 get set to input _during_ a reset.

When reading the PS, I come to a different conclusion:

My interpretation of these parts of the PS is that the GPIOs will retain their state (input, output, etc.) during a reset.

Can someone shed some light on this?

Best Regards

Tobias

[Jared]

Hi,

This depends on the type of reset. It will retain its value through a wake up from system off and a soft reset, however a pin reset and a power cycle will put its state back to default. See this post.

regards

Jared 

EDIT: This is not correct, see my last comment.

[Tobias Schneider]

Hi,

in our use-case the nRF52 is in "SYSTEM ON" mode and gets reset (and held in reset) via the Reset pin. The question is how GPIOs which are configured to output behave in this case.

Is it possible that they continue to behave as output during the reset if configured via the "PIN_CNF" registers, but revert to input if they were configured via the "DIR" register?

Best
Tobias

[Jared]

Hi Tobias,

I'm very sorry for the confusion, but after testing this myself I see that it's only SYSTEM OFF that keeps some registers retained, all other forms of reset will put the peripheral and its assigned pins to its reset value. I do agree that this can be quite confusing in the product specification and I will report this. Hopefully, a future version of the product specification will clarify this point much better.

best regards

Jared 

[Örjan]

Is this an issue for nrf52840 (soc rev 2) as well? We have been struggling a while trying to find out what we are doing wrong losing gpio cnf register content during a soft reset sequence.

I cannot find any related errata, so if there is a bug, is it related to documentation or to the chip?

[Jared]

So it's important to note that this is not an issue nor a bug, but rather a section in the Product specification that could be explained better. The GPIO_CNF will be reset after a soft reset as the GPIO peripheral itself is reset after a soft reset. This is the case for all resets except from reset from SYSTEM OFF. 

[Tobias Schneider]

Thanks!

[Örjan]

Ok, thank's for the clarification! My interpretation is that either the gpio cnf register is NOT a retained register OR there is (currently?) no reset situation exposing any difference in behavior between a gpio retained and a gpio non-retained register; Either all or no gpio registers are reverted to reset state, and the former would apply for all cases but wake up from system off.

[Jared]

The GPIO_CNF register is retained if there is a reset from SYSYTEM OFF, in all other cases it's reset to it's default value along with the other GPIO registers.