ESD protection for SWD

[Deimantas]

Hi,

Need ESD protection recommendation for NRF51822. While testing nrf51822, we noticed that when SWDCLK gets static dicharge over 900 V, nrf51822 reboots and current consumption increases to ~1.2 mA or only current consumption increases to ~1.2 mA. Found out that in such case, nrf51822, goes to debug mode, and thats why current consumption increases.

Is there any way to detect from application that nRF51822 is in debug mode? Or maybe there is other way to solve this? 470ohm resistor to ground on SWDCLK doesn't help. Nnly helps when SWDCLK connected to ground directly or with 0R resistor, but then we can't program nrf51822.

[Asbjørn]

You could tie the pin directly to ground on the final product. During development you could have a different implementation/component that would allow you to program the chip. That would allow you to develop normally and also replace the component to ground if you feel that is necessary for the application.

[Locky]

Thanks Simon, our jig has a voltage set to 3.3V so we are ok on that side. I've scoped the lines which show a T(rise) =180nsec(max) and T(fall)=200nsec(max). According to the J-Link Lite data sheets the T(rise) and T(fall) timing is <= 20nsec.

However when testing on a PCB without any ESD protection, the T(rise) and T(fall) time is still 48nsec, or double the specification. I think I'll make a support case on this.