GPIO setup parameters for AoA Antenna switching

[benkokes]

I have an issue with getting the I/Os correctly setup for antenna switching.

I am running the radio_test example code with the following modifications. 

So far, I have the following code for the GPIO setup:

//Defines are at top of file
#define ANT1 NRF_GPIO_PIN_MAP(0,17)
#define ANT2 NRF_GPIO_PIN_MAP(1,8)
#define ANT3 NRF_GPIO_PIN_MAP(1,7)
#define ANT4 NRF_GPIO_PIN_MAP(1,6)

//other support code

//Pin config
nrf_gpio_pin_clear(ANT1);
nrf_gpio_cfg_output(ANT1);
nrf_gpio_pin_clear(ANT2);
nrf_gpio_cfg_output(ANT2);
nrf_gpio_pin_clear(ANT3);
nrf_gpio_cfg_output(ANT3);
nrf_gpio_pin_clear(ANT4);
nrf_gpio_cfg_output(ANT4);

//DFE pin config
NRF_RADIO->PSEL.DFEGPIO[0] = ANT1; //(P0.17)
NRF_RADIO->PSEL.DFEGPIO[1] = ANT2; //(P1.08)
NRF_RADIO->PSEL.DFEGPIO[2] = ANT3; //(P1.07)
NRF_RADIO->PSEL.DFEGPIO[4] = ANT4; //(P1.06)

NRF_RADIO->SWITCHPATTERN = 1; //Only P0.07 active
NRF_RADIO->SWITCHPATTERN = 2; //Only P1.08 active
NRF_RADIO->SWITCHPATTERN = 4; //Only P1.07 active
NRF_RADIO->SWITCHPATTERN = 8; //Only P1.06 active

NRF_RADIO->DFEMODE = RADIO_DFEMODE_DFEOPMODE_AoA;
NRF_RADIO->DFECTRL1 = 10 << RADIO_DFECTRL1_NUMBEROF8US_Pos | 
                       1 << RADIO_DFECTRL1_DFEINEXTENSION_Pos;

Then in the radio_test.c file, I include in the function radio_rx( ...)

uint32_t g_iq_packet[RADIO_MAX_PAYLOAD_LEN];

void radio_rx(....)
{
//orig example code still exists here, only not shown
    NRF_RADIO->DFEPACKET.PTR = (uint32_t)g_iq_packet;

}

From a board running the radio_test example, I issue the 'start_tx_modulated_carrier' command the immediately issue the 'start_rx" command on a seperate DK also running the radio_test example with the above modifications.

I expected to see a short duration square wave on each of the antenna GPIO pins, so, 4 square waves cascading in time. However from my logic analyzer capture, you can clearly see that is not the case.

How should I be setting up the config registers to fire each of the pins.  Nothing else is connected to the board except the logic analyzer.

Also, how do I correlate the IQ data from the DFEPACKET.PTR to the specific antenna?

[Simonr]

Hi everyone!

Glad to see such a lively discussion on direction-finding here on the forum. I just wanted to say that Dmitry is doing a great job explaining direction finding in this post, and can confirm that what he's saying is correct.

Best regards,

Simon

[Hardik.Harpal]

Hi Simonr,

Piotr said:

One more thing related with mapping of antennas to samples. In all diagrams there is an information that after reference period there is a switch-slot/sample-slot pairs sequence. Unfortunately there is a gap. The gap lasts for single switch-slot. So first sample you receive is taken in first sampling-slot. After that each sample is stored in configured delay. 

That does matter for mapping of antennas to samples, especially in case of oversampling. 

Let take for example following settings:

• NUMBEROF8US=3 ->24us
• TSWITCHSPACING=2us
• TSAMPLESPACING=250ns
• TSAMPLESPACINGREF=250ns

Number of samples would be: Ref period 8us/0.25 = 32, switch-period 12/0.25=48

First sample from switch-period would be taken in first sampling slot, so you would have a time delay of 4 samples (1us - swtich slot).

After that delay you would have samples: 

• 4 samples taken in 1st sampling-slot (antenna 1)
• 4 samples taken in 2nd switch-slot (antenna 2)
• 4 samples taken in 2nd sampling-slot (antenna 2)
• 4 samples taken in 3rd switch-slot (antenna 3)

As said in quote, Is it correct to say that first sample after reference period aligns to first sampling slot. so there will be 1us delay(switch slot time = switch spacing/2) for first sample after reference period?

If so than in out of 12us switching-sampling period only 11us will be samples so there will be 11/0.25 = 44 samples only instead of 48 as said in above quote. Am I correct?

But actually I am getting 48 samples with this setting what is correct understanding regarding switching pattern and sampling order with respect to it.

[Simonr]

Hi

Piotr is one of the firmware engineers here at Nordic, and has experience in this field, so what is said in this quote is reliable. Please note that the "first sample from switch-period would be taken in first sampling slot, so you would have a time delay of 4 samples". So no, you would not have 44 samples instead of 48, but you will have a delay of 1us before the samples are taken.

Best regards,

Simon

[Hardik.Harpal]

Hi,

I know his wording is reliable  and same was written in White Paper "The hardware always aligns the first IQ sample in the first sample slot."

But I am not getting that time delay understanding, can you clear my understanding?

in 24 us even radio start sampling on first edge of sample slot duration maximum 45 samples can be taken.

0.25us	Guard Period
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
4.25	Reference Period	Sample 1
4.5		Sample 2
4.75		Sample 3
5		Sample 4
5.25		Sample 5
5.5		Sample 6
5.75		Sample 7
6		Sample 8
6.25		Sample 9
6.5		Sample 10
6.75		Sample 11
7		Sample 12
7.25		Sample 13
7.5		Sample 14
7.75		Sample 15
8		Sample 16
8.25		Sample 17
8.5		Sample 18
8.75		Sample 19
9		Sample 20
9.25		Sample 21
9.5		Sample 22
9.75		Sample 23
10		Sample 24
10.25		Sample 25
10.5		Sample 26
10.75		Sample 27
11		Sample 28
11.25		Sample 29
11.5		Sample 30
11.75		Sample 31
12		Sample 32
12.25	Switch Slot 1
12.5
12.75
13
13.25	Sample Slot 1	Sample 33
13.5		Sample 34
13.75		Sample 35
14		Sample 36
14.25	Switch Slot 2	Sample 37
14.5		Sample 38
14.75		Sample 39
15		Sample 40
15.25	Sample Slot 2	Sample 41
15.5		Sample 42
15.75		Sample 43
16		Sample 44
16.25	Switch Slot 3	Sample 45
16.5		Sample 46
16.75		Sample 47
17		Sample 48
17.25	Sample Slot 3	Sample 49
17.5		Sample 50
17.75		Sample 51
18		Sample 52
18.25	Switch Slot 4	Sample 53
18.5		Sample 54
18.75		Sample 55
19		Sample 56
19.25	Sample Slot 4	Sample 57
19.5		Sample 58
19.75		Sample 59
20		Sample 60
20.25	Switch Slot 5	Sample 61
20.5		Sample 62
20.75		Sample 63
21		Sample 64
21.25	Sample Slot 5	Sample 65
21.5		Sample 66
21.75		Sample 67
22		Sample 68
22.25	Switch Slot 6	Sample 69
22.5		Sample 70
22.75		Sample 71
23		Sample 72
23.25	Sample Slot 6	Sample 73
23.5		Sample 74
23.75		Sample 75
24		Sample 76
		Sample 77

[Simonr]

I'm sorry, but I'm not sure I understand what you mean by this, or how to explain this delay any further than it being a delay before the sampling starts. As this ticket is rather old and long, please create a new ticket where you describe your question in detail (and link to this thread if relevant).

Best regards,

SImon