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High Sample Rate with ADC and SoftDevice

I am trying to sample the ADC every 2ms. I notice lots of slowness with BLE advertising and typically can't connect to device over BLE when sampling. I am using PPI, configuring, and starting before the softdevice is enabled.

  1. Should nRF51822 be capable of reading ADC every 1ms to 2ms reliably?

  2. Should I move all the PPI configuration to after the softdevice is enabled and be using the sd_ppi functions?

Thanks!

Edit: Headline, format, added tags.

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  • I note that it is not possible to use the ARM core to 'sample' the ADC value regularly enough, BUT Is it possible to use the EasyDMA in the SPIS devices?

    My proposal:

    The ADC would be set to capture a value using the PPI and its START task and a timer, this gives the regular sample, but not the ability to 'save' the value before it is overwritten.

    To 'save' the data, the SPIS could be set to loop back upon itself, with the TXDPTR set to the ADC result address, and the MAXTX set to 1 for 8-bit samples and 2 for 10 or 9 bit samples. The RXDPTR would then be set to a normal RAM address with a normal buffer size for example 256 to capture 256 8-bit samples.

    Then you connect the MOSI and MISO pins, and the SCK to a suitable clock source (maybe the Master's clock, and then finally connect the CSN to a GPIO that is triggered using the PPI to make a suitably long chip enable signal.

    I know this is convoluted, but the SPIS is the only memory bus master other than those used by the SoftDevice. Is this a feasible, if awkward, solution to regular sampling whilst the SoftDevice is enabled?

    It would be useful to have some feedback to this proposal to help me make my product selection as the ADC capability is one of the nRFs key features (aside from its Bluetooth capabilty).

    Yours,

    Peter Myerscough-Jackopson

  • Hi Peter

    Thanks for your proposal. I think your proposal is very good. I can not see why this should not work. I see this as a timer that is enabled with three compare registers:

    One compare register triggers the ADC sampling, i.e. CC[0] -> PPI[0] -> ADC->START

    Second compare register triggers SPI TX, i.e CC[1] -> PPI[1] -> GPIOTE[1]. GPIOTE[1] is gonfigured for a GPIO pin that is looped to the SPIS CSN pin. If you were doing 8-bit sampling, you would perhaps have this compare register trigger 25us after triggering the first compare register as it takes 20us to sample with 8-bit resolution.

    Third compare register creates the SPI clock by toggling a pin that is looped to SPIS SCK pin, i.e. CC[2] -> PPI[2] -> GPIOTE[2]

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  • Hi Peter

    Thanks for your proposal. I think your proposal is very good. I can not see why this should not work. I see this as a timer that is enabled with three compare registers:

    One compare register triggers the ADC sampling, i.e. CC[0] -> PPI[0] -> ADC->START

    Second compare register triggers SPI TX, i.e CC[1] -> PPI[1] -> GPIOTE[1]. GPIOTE[1] is gonfigured for a GPIO pin that is looped to the SPIS CSN pin. If you were doing 8-bit sampling, you would perhaps have this compare register trigger 25us after triggering the first compare register as it takes 20us to sample with 8-bit resolution.

    Third compare register creates the SPI clock by toggling a pin that is looped to SPIS SCK pin, i.e. CC[2] -> PPI[2] -> GPIOTE[2]

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