High Sample Rate with ADC and SoftDevice

[Chris]

I am trying to sample the ADC every 2ms. I notice lots of slowness with BLE advertising and typically can't connect to device over BLE when sampling. I am using PPI, configuring, and starting before the softdevice is enabled.

1. Should nRF51822 be capable of reading ADC every 1ms to 2ms reliably?

2. Should I move all the PPI configuration to after the softdevice is enabled and be using the sd_ppi functions?

Thanks!

Edit: Headline, format, added tags.

[Lucas]

Stefan,

I will attempt to implement and keep you posted. To make it work I think I will need to use 2 times, several PPI's, and the ADC. I think that the clock must be generated using one dedicated timer, and the timing for adc conversion and spi must be done using another timer. Of course, this implementation is clunky and will use increased power. I look forward to the rev3. Could you explain a little more about the current implementation and how it will be changed for my understanding? Right now a ble_evt is a background task (of highest priority) and therefore block out all other interrupts from interrupting it? Is the ble_evt a software interrupt or a hardware interrupt? Also, where can i find code for working with the timer peripherals. Does nordic have any documents outlining restricted priority levels for peripherals?

[Stefan Birnir Sverrisson]

The stack generates software interrupts with priority 2 to signal the application of events. So to make a peripheral interrupt handler (e.g. ADC interrupt handler) have higher priority than any BLE callback events you must set the priority of your peripheral interrupt handler to 1 (i.e APP_IRQ_PRIORITY_HIGH). However, when a peripheral interrupt handler has priority APP_IRQ_PRIORITY_HIGH, you can not call any softdevice function from the peripheral interrupt handler, starting with sd_*. You can realize the priority structure in S110 Softdevice Specification v1.2, section 10.2. For nRF51 rev 2, the CPU is blocked during the whole radio event. For nRF51 rev 3, the CPU should be available after each transmitted packet. I expect this to allow 5kHz-10kHz maximum sampling rate for the ADC, but we will have to see what the actual specification for rev 3 reveals.

[Lucas]

Stefan,

After reading the data sheet more thoroughly it is not clear to me how this will be possible.

"As long as the semaphore is available the SPI slave can be granted multiple transactions one after the other. If the CPU is not able to reconfigure the TXDPTR and RXDPTR between granted transactions, the same TX data will be clocked out and the RX buffers will be overwritten."

My interpretation of this is that everytime chip select is toggled RXPTR and TXPTR will start pulling from their original memory location. This is ideal for the TXPTR, but not the RXPTR. Essentially, this transaction will overwrite the first element in the RX buffer over and over with the adc value put out from the TXPTR.....

[Lucas]

Stefan, I am also confused about your previous statement.

"For nRF51 rev 3, the CPU should be available after each transmitted packet. I expect this to allow 5kHz-10kHz maximum sampling rate for the ADC, but we will have to see what the actual specification for rev 3 reveals."

If the CPU becomes available after each transmitted packet and each packet is ~1ms long wouldn't that yield a 1kHz sampling rate? My company is in the process of making serious architectural decisions and this information is extremely important.

[Peter Myerscough-Jackopson]

Lucas, although I have not done the work, using the SPIS unit you would configure the RX to be many samples long, and the TX to be just a single sample long from one ADC location. The PPI would then enable the transfer of just one ADC measurement, by pulsing the SPIS CS/EN pin for just a single transfer period. This would mean the RX transfer would receive one measurement, but not complete, whilst the TX would send one measurement. The RX transfer would therefore slowly fill up the buffer it is given for its transfer, whilst the TX would repeatedly read the ADC result register location.

I hope this helps in clarifying the concept of using the SPIS to achieve regular sampling. The rev3 silicon will not require the SPIS to achieve higher sampling rates 5-10kHz, but as Stefan says we are only guessingwaiting in that regards.

Peter