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can not control P1 with nrf5340_dk_nrf5340_cpuappns configuration

I can control GPIO P0,but can't control P1, when I load project with nrf5340_dk_nrf5340_cpuappns configuration.

If I load project with nrf5340_dk_nrf5340_cpuapp configuration, I can control both P0 and P1.

Why there is no P1 in nrf5340_dk_nrf5340_cpuappns spm configuration?

I tried to add P1 config manually in spm.c and Kconfig, but I still couldn't control P1.

The source code is based on ncs v1.2.0,and is a continuation of the following problem https://devzone.nordicsemi.com/f/nordic-q-a/58966/is-there-any-sample-for-spi-based-on-nrf5340

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  • Hi,Simon

    Thank you for your answer

    Yes,I later found that there are some pins for special functions.

    P0.02 P0.03 ->NFC1 NFC2(modify NRF_UICR_S->NFCPINS, these pins can be configed as gpio)

    P0.04 ->AIN0 (disable adc in devicetree, this pin can be configed as gpio)

    P0.19 P0.20 P0.21 P0.22->Debug uart log output (maintain uart function)

    P0.13 P0.14 P0.15 P0.16 P0.17 P0.18 -> QSPI, these pins can be configed as gpio

    P0.08 P0.09 ->I configed these pins as spi port.If disable spi,they can be controled as gpio.

      

    But I still don't know how to control the level flip of the following pins

    P0.10 P0.25 P0.26 (I still don't know what these pins are configured to do)

    P0.00 P0.01->XL1 XL2 (how to config as gpio.I have tried to config to use RC Oscillator in menuconfig but it failed to compile)

  • Hi,Simon

    Thanks to the help of Smile(Nordic FAE), we found the reason why P0.10 P0.25 P0.26 cannot be controlled.

    In ncs\zephyr\boards\arm\nrf5340_dk_nrf5340\nrf5340_cpunet_reset.c  P0.10 P0.12 P0.25 P0.26 use for uart.

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