I can control GPIO P0,but can't control P1, when I load project with nrf5340_dk_nrf5340_cpuappns configuration.
If I load project with nrf5340_dk_nrf5340_cpuapp configuration, I can control both P0 and P1.
Why there is no P1 in nrf5340_dk_nrf5340_cpuappns spm configuration?
I tried to add P1 config manually in spm.c and Kconfig, but I still couldn't control P1.
The source code is based on ncs v1.2.0,and is a continuation of the following problem https://devzone.nordicsemi.com/f/nordic-q-a/58966/is-there-any-sample-for-spi-based-on-nrf5340
I found not all P0 can be controled.Only P0.07,P0.11,P0.23,P0.24,P0.27,P0.28,P0.29,P0.30,P0.31 can be control as GPIO.
By modifying the spm.c Kconfig file, I can already control the output of P1.
But I still can't find out why I can't control part port of P0( only P0.07,P0.11,P0.23,P0.24,P0.27,P0.28,P0.29,P0.30,P0.31 can be controled).
For some pins, a solder bridge needs to be cut in order to use it as normal GPIO. Check out nRF53 PDK Solder bridge configutation for a more detail description.
Thanks to the help of Smile(Nordic FAE), we found the reason why P0.10 P0.25 P0.26 cannot be controlled.
In ncs\zephyr\boards\arm\nrf5340_dk_nrf5340\nrf5340_cpunet_reset.c P0.10 P0.12 P0.25 P0.26 use for uart.