number of I/Q samples and the sampling offset

[tc_2020]

Hello,

I am testing direction finding over nRF5340 PDK.

I didn't have antenna array yet, but I think that's equivalent to signal received at 90 degree.

I have two questions:

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1. number of I/Q samples

I have configured

• sampling interval at REF to 125ns
• sampling interval at switch period to 125ns
• CTE length to 24 us 
• Switching interval to 2 us

I consider the number of samples to transfer is calculated as:  8/0.125 + (24-12)/2 )/0.125 = 64 + 48 = 112 samples. 

However when I read the AMOUNT register, it gives 160: which I assume it calculated as 8/0.125 + (24-12)/0.125 = 64 + 96 = 160 samples.

This means the sampling is not only happening during sampling slot, but both the switch slot and sampling slot. Is this what chip is doing?

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2. sampling offset

I have plotted the result as shown in figure below: 

The x axis is time, the data starts at 4us indicating the start of reference period. I mapped the data from 4us to 24 us with 0.125 spacing. This maybe is wrong but I don't know for the moment what is the right timestamp for the I/Q sample data.

You can see there is a disconnection from 12us when the reference period ends. Is this the sample offset indicated in the production specification? I configured to 3 (3@16M = 0.1875us, which is probably not enough. I have shift the right part by 1us on the timing, which makes the wave looks continuously.

Could someone help me to understand when those samples are taken exactly ? Thanks a lot!

Tengfei

[Dmitry]

Hi,

tc_2020 said:

This means the sampling is not only happening during sampling slot, but both the switch slot and sampling slot. Is this what chip is doing?

Yes, that's true.

tc_2020 said:

You can see there is a disconnection from 12us when the reference period ends. Is this the sample offset indicated in the production specification?

There is an 1-us gap after reference period, it's not related to sampling offset. The documentation is not clear about this point, but there is a white paper with better description.

You don't need to figure out an exact times at this moment. When you'll have a prototype hardware, take a measurement at 0.125us rate and you will see the best sampling point for your array and switch IC.

[tc_2020]

Hi Dmitry,  Thanks for your quick response!

Just read the white paper you provided, so for the 1-us gap, I think it's explained in section 3.2 First IQ samples.  According to Figure 11 in the white paper, the gap is the TSAMPLESPACINGREF + TSWITCHSPACING/2 = 1.125 to my case.

If this is true, and according to your answer of my first question, why the total sampling number is still 160, rather than 160-8 (8 samples in the first switch slot).