Build zephyr.elf versus Build solution

[Learner]

I can see in Segger Embedded Studio v4.52 under the Build Tab, there are two methods to build the project.

1- Build > Build zephyr/zephyr.elf

2- Build > Build solution

What is the difference between the two methods?

Kind regards

[Heidi]

Hi again!

So, first of all, to answer your questions about SPI:

You are right, I did not catch that part. I have sent a message to the Nordic developer that has written this, but since they are based in LA I won't have an answer on this until tomorrow.

I just received an answer about this.

"An index representing the peripheral’s chip select line number. (If there is no chip select line, 0 is used.)"

The spi1 node has a cs-gpios property, which means that the unit addresses for node a and b (0 and 1 respectively) are indexes into the cs-gpios array (an index representing the peripheral's chip select line number). The spi1 node has no cs-gpios, so node c has no chip select configured in the device tree, and therefore its unit address is left at 0 (if there is no chip select line, 0 is used). 

In all your overlay examples you're still instantiating the ADC peripheral, which we don't want to do. 

This is the template you want to follow:

/ {
    n: node {
        compatible = " ";
        io-channels = <&adc 4>;
	    label = "AIN_0";
	};
};

The forward slash indicates the root node and is very important to include.

To include multiple ADC io-channels, just refer to the adc-node each time like this (not &adc5 and &adc7):

io-channels = <&adc 26>, <&adc 28>;

and if you want to use a different compatible property for the two nodes, you need to create two separate nodes like this:

/ {
    n: node_a {
        compatible = " ";
        io-channels = <&adc 26>;
	    label = "AIN_5";
	};
	
    n: node_b {
        compatible = " ";
        io-channels = <&adc 28>;
	    label = "AIN_7";
	};
};

For you question about voltage-divider

The lower leg is not a resistor, but the other one is a resistor? Or are you using a capacitive divider where both elements are capacitors?

For your binding question, yes this is the correct way to do it, using the label you defined in the node.

adc_dev_5 = device_get_binding("AIN_5");

adc_dev_7 = device_get_binding("AIN_7");

To do the binding for the two analog inputs, this is how to do it for AIN_5 and AIN_7 respectively.

device_get_binding(DT_IO_CHANNELS_LABEL_BY_IDX(DT_NODELABEL(n),0))
device_get_binding(DT_IO_CHANNELS_LABEL_BY_IDX(DT_NODELABEL(n),1))

Best regards,

Heidi

[Learner]

Thank you Heidi for your help.

Heidi said:

The spi1 node has a cs-gpios property, which means that the unit addresses for node a and b (0 and 1 respectively) are indexes into the cs-gpios array (an index representing the peripheral's chip select line number). The spi1 node has no cs-gpios, so node c has no chip select configured in the device tree, and therefore its unit address is left at 0 (if there is no chip select line, 0 is used).

I can see what you are saying here. However, it is still rather confusing because looking at the definition of sub-node (a) and sub-node (c) they are identical but in fact they are telling us different information about the sub-node.

Learner said:

* a: spi-dev-a@0 {
* reg = <0>;
* };

Learner said:

* c: spi-dev-c@0 {
* reg = <0>;
* };

Heidi said:

This is the template you want to follow:

This is how my overlay file looks,

/ {
n: node {
compatible = " ";
io-channels = <&adc 4>;
label = "AIN_0";
};
};

&pwm0 {
ch0-pin = < 29 >;
};

The project now loads but I am getting build errors. I am including the build log and the devicetree_unfixed.h.

Heidi said:

The lower leg is not a resistor, but the other one is a resistor? Or are you using a capacitive divider where both elements are capacitors?

Yes, the upper leg is a resistor and the lower leg is a capacitor.

Kind regards

Mohamed