Build zephyr.elf versus Build solution

[Learner]

I can see in Segger Embedded Studio v4.52 under the Build Tab, there are two methods to build the project.

1- Build > Build zephyr/zephyr.elf

2- Build > Build solution

What is the difference between the two methods?

Kind regards

[Learner]

Heidi said:

Learner said:

The link above shows spi-dev-a@0 has a chip select line defined in the parent node, yet 0 is used as index.

"An index representing the peripheral’s chip select line number. (If there is no chip select line, 0 is used.)

Yes, the SPI controller, which is the parent node, has a chip. But the SPI device, the child node, does not have a chip select. Therefore the unit-address is 0. 

So, if there is no chip select line in that specific node 0 is used.

I would have accepted your answer if it was not for the definition of node b just below node a. Node b has no chip select line but the index used is NOT 0 but 1. See below an extract from spi.h.

/**
* @brief Does a SPI device have a chip select line configured?
* Example devicetree fragment:
*
* spi1: spi@... {
* compatible = "vnd,spi";
* cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
* <&gpio2 20 GPIO_ACTIVE_LOW>;
*
* a: spi-dev-a@0 {
* reg = <0>;
* };
*
* b: spi-dev-b@1 {
* reg = <1>;
* };
* };
*
* spi2: spi@... {
* compatible = "vnd,spi";
* c: spi-dev-c@0 {
* reg = <0>;
* };
* };
*
* Example usage:
*
* DT_SPI_DEV_HAS_CS_GPIOS(DT_NODELABEL(a)) // 1
* DT_SPI_DEV_HAS_CS_GPIOS(DT_NODELABEL(b)) // 1
* DT_SPI_DEV_HAS_CS_GPIOS(DT_NODELABEL(c)) // 0
*
* @param spi_dev a SPI device node identifier
* @return 1 if spi_dev's bus node DT_BUS(spi_dev) has a chip select
* pin at index DT_REG_ADDR(spi_dev), 0 otherwise
*/

Heidi said:

Okay, so for the node for AIN_5, you can use the voltage-divider compatible property.

Great news! 

So, how would the overlay file look? and where must I store the .yaml file? Can I put it in the same folder as the prj.conf file?

Kind regards

Mohamed

[Learner]

Please ignore my question about the yaml file.

I have had an attempt at creating this overlay file. Would this overlay file do the job?

&adc {
   compatible = "voltage-divider";

   adc5: {
      label = "AIN_5";
   }

   adc7: {
      label = "AIN_7";
   }

   n: node {
      io-channels = <&adc5 26>, <&adc7 28>;
      io-channel-names = "FOIL", "STRAP";
   };
};

Looking at the yaml file, line 21 is referring to Resistance of the lower leg of the voltage divider. But in our case the lower is not a resistance but a capacitance. Is this ok?

Assuming I can use the "voltage-divider"compatible property, I can do the binding using this

 adc_dev_5 = device_get_binding("AIN_5");                                                                               adc_dev_7 = device_get_binding("AIN_7");

Please confirm if I am on the right path...

Kind regards

Mohamed

[Learner]

Learner said:

io-channels = <&adc5 26>, <&adc7 28>;

The numbers 26 and 28 refer to the pin numbers on PORT0 used for AIN5 and AIN7.

[Learner]

Hi Heidi,

I give up. I tried few flavours of the overlay file and none worked. The project always fail to load.

# Method 1:
&adc {
# compatible = "nordic,nrf-saadc";
 compatible = "voltage-divider";

 adc5:adc@... {
 label = "AIN_5";
 }

 adc7:adc@... {
 label = "AIN_5";
 }

 n: node {
 io-channels = <&adc5 26>, <&adc7 28>;
 io-channel-names = "FOIL", "STRAP";
 };
};

# Method 2:
adc0: adc@4000E000 {
compatible = "nordic,nrf-saadc";
# compatible = "voltage-divider";
label = "ADC_0";
};

n: node {
io-channels = <&adc0 4>;
io-channel-names = "AIN_0";
};

Kind regards

Mohamed

[Heidi]

Hi again!

So, first of all, to answer your questions about SPI:

You are right, I did not catch that part. I have sent a message to the Nordic developer that has written this, but since they are based in LA I won't have an answer on this until tomorrow.

I just received an answer about this.

"An index representing the peripheral’s chip select line number. (If there is no chip select line, 0 is used.)"

The spi1 node has a cs-gpios property, which means that the unit addresses for node a and b (0 and 1 respectively) are indexes into the cs-gpios array (an index representing the peripheral's chip select line number). The spi1 node has no cs-gpios, so node c has no chip select configured in the device tree, and therefore its unit address is left at 0 (if there is no chip select line, 0 is used). 

In all your overlay examples you're still instantiating the ADC peripheral, which we don't want to do. 

This is the template you want to follow:

/ {
    n: node {
        compatible = " ";
        io-channels = <&adc 4>;
	    label = "AIN_0";
	};
};

The forward slash indicates the root node and is very important to include.

To include multiple ADC io-channels, just refer to the adc-node each time like this (not &adc5 and &adc7):

io-channels = <&adc 26>, <&adc 28>;

and if you want to use a different compatible property for the two nodes, you need to create two separate nodes like this:

/ {
    n: node_a {
        compatible = " ";
        io-channels = <&adc 26>;
	    label = "AIN_5";
	};
	
    n: node_b {
        compatible = " ";
        io-channels = <&adc 28>;
	    label = "AIN_7";
	};
};

For you question about voltage-divider

The lower leg is not a resistor, but the other one is a resistor? Or are you using a capacitive divider where both elements are capacitors?

For your binding question, yes this is the correct way to do it, using the label you defined in the node.

adc_dev_5 = device_get_binding("AIN_5");

adc_dev_7 = device_get_binding("AIN_7");

To do the binding for the two analog inputs, this is how to do it for AIN_5 and AIN_7 respectively.

device_get_binding(DT_IO_CHANNELS_LABEL_BY_IDX(DT_NODELABEL(n),0))
device_get_binding(DT_IO_CHANNELS_LABEL_BY_IDX(DT_NODELABEL(n),1))

Best regards,

Heidi