TWI SDA SCL held low during reset when using TWIS

[pavel.kucera]

Hi to community!

I have a trouble with nRF52840 when using TWIS. I initialize the peripheral by below code. If the device is reset using default pin 18 by the external controller, SDA and SCL pins are held low, so the communication with other sensors on bus is broken. Is there a way for the mentioned signals to be in Hi-Z during reset? 

nrf_gpio_cfg(26U, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0D1, NRF_GPIO_PIN_NOSENSE);
nrf_gpio_cfg(27U, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0D1, NRF_GPIO_PIN_NOSENSE);
const nrf_drv_twis_config_t config =
{
  .addr = {0x0BU, 0U},
  .scl = 27U,
  .sda = 26U,
  .scl_pull = NRF_GPIO_PIN_PULLUP,
  .sda_pull = NRF_GPIO_PIN_PULLUP,
  .interrupt_priority = APP_IRQ_PRIORITY_HIGH
};
nrf_drv_twis_init(&f_i2c, &config, i2c_event_handler);

It behaves in same way if the first two lines (nrf_gpio_cfg) are omitted.

Thank in advance for any help with this problem.

[Vidar Berg]

Hi,

Does this cause the TWI master to get stuck in a bad state? I think it's usually the other way around (ref. blocke I2C bus)  nRF pin states are undefined during reset, so I'm afraid we can't guarantee a Hi-Z state.

Best regards,

Vidar

[pavel.kucera]

The main problem is with the fact the bus is held low while nRF held in reset state via pin, other slaves on the bus cannot be commanded in that time including HW watchdog sitting as slave on I2C bus. I2C state machine of master is not the issue here. Even in case master is stuck, I cannot do bit-banging with SCL to release the bus, as the lines are driven low by nRF.

[Vidar Berg]

Does the nRF know ahead of time if the master is going to assert the reset line? In that case, you could try disabling the TWIS and re-configure the GPIOs back to their reset value before the reset takes place.

[pavel.kucera]

If the nRF knew about need to reset ahead, there wouldn't be need to issue reset via GPIO pin but will use some sort of SW reset instead. It seem similar to problem described here with UART. The difference here is that UART TX pin is output (push-pull or open-drain), but TWIS SCL and SDA pins should be inputs at least between transactions but during reset the change to outputs. I've never seen such behavior during my carreer before.

[Vidar Berg]

I guess the IO state may depend on when the board in reset.

[pavel.kucera]

From my point of view this discussion leads to nowhere. Could you please guide me to the documentation, where one could read that pin states are undefined during reset? So I can tell that to customer, it is not my fault as a FW programmer, that those pins are low during reset?

[Vidar Berg]

 Sorry. But are you able to use workaround you already suggested? As I indicated earlier, the pin state is not defined in reset. The documented reset values applies to when the internal reset sequence is completed (ie after you release the reset line).  Although, I do understand it might be surprising that the pins become configured as outputs in this case.