Reset after sd_power_system_off in Non Debug mode

[exsurgo_ankit]

Hello,

We have a custom board designed using the ublox Anna B112 module which uses NRF52832. We are using it in open CPU mode and running our custom firmware. 

The VDD is 1.8V in our case. Whenever I have tried to enter deep sleep mode via 

sd_power_system_off() OR

nrf_power_system_off() OR

nrf_pwr_mgmt_shutdown(NRF_PWR_MGMT_SHUTDOWN_GOTO_SYSOFF) OR

NRF_POWER->TASKS_LOWPWR = 1; NRF_POWER->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;

The system resets right after. The RESETREAS register reads zero, suggesting that a power on or a brownout reset. I understand that 1.7V is minimum operational voltage.  My questions are:

1. How long does the VDD need to drop below that to trigger the reset?

2. How do I troubleshoot this issue? I have probed the VDD line using an oscilloscope have noticed a drop close to 1.7V for about 20 uSec.

I have reviewed all the threads on the forum on this issue. Ensured that the test is not in Debug mode, power cycled the unit, added an infinite loop after the call. 

Regards

[exsurgo_ankit]

Hello,

Here is an update which hopefully helps someone facing a similar issue. 

The issue doesn't seem to have anything to do with the 1.8V VDD. We have identified that it stops occurring when we unplug the hardware from a TTL UART connected to the PC. We do not have level shifters on the UART lines so the external TTL circuitry is causing the issue.

My question for Nordic is, what happens if an IO is at a voltage above VDD while the system is trying to enter deep sleep mode?

Regards

[run_ar]

What is the actual IO voltage?

Please remember the Absolute maximum ratings for IO voltage as stated in the product specification:

I/O pin voltage
		Min	Max
VI/O, VDD ≤ 3.6 V		-0.3	VDD + 0.3	V
VI/O, VDD > 3.6 V		-0.3	3.9	V