Hi:
we set p21 as Hardware Reset Pin by config UICR.PSELRESET[0] = UICR.PSELRESET[0] = 21
when we use these code to check halt state, but always get DBG_HCSR zero value.
// put to debug
if (!swd_init_debug()) {
return false;
}
// Enable debug
if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN )) {
return false;
}
// just debug, clear reset flags
swd_write_word(0x40000400, 0x000F000F);
// hardware reset, pseudo-code
set p21 == low
wait 1ms
set p21 == High
// just debug
uint32_t value = 0;
// RESETREAS ==> 0x40000000 + 0x400
swd_read_word(0x40000400, &value);
// wait bkpt halt( end of MUT main())
if (!swd_wait_until_halted()) {
return false;
}
we check the RESETREAS register: it's Reset from pin-reset detected
in NRF52832 flash, use No SoftDevice, just like this code:
int main()
{
// here do something
.........
// important: SWD host used wait this function run finished and ok.
__ASM volatile ("movs r0, #0"); // set R0 to 0 show success
__ASM volatile ("bkpt #0"); // halt MCU
return 0;
}
when Hardware Reset happened, it should halt on bkpt instruction. when check DBG_HCSR, it should return S_HALT flag. But read DBG_HCSR, got 0x00.
Compare STM32 MCUs, it's working fine.
What's special NRF52832 Hardware Reset Pin with SWDIO/SWCLK pins? In the document, SWJ-DP will No effect by Hardware Reset Pin Reset behavior.
what's about core debug registers? like DHCSR, DEMCR....
