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The NRF52832 did not halt after hardware Reset Pin Reset.

Hi:

    we set p21 as Hardware Reset Pin by config UICR.PSELRESET[0] = UICR.PSELRESET[0]  = 21

    when we use these code to check halt state, but always get DBG_HCSR zero value.

    // put to debug
    if (!swd_init_debug()) {
        return false;
    }

    // Enable debug
    if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN )) {
        return false;
    }

    // just debug, clear reset flags
    swd_write_word(0x40000400, 0x000F000F);
    // hardware reset, pseudo-code
set p21 == low
wait 1ms
set p21 == High

    // just debug
    uint32_t value = 0;
    // RESETREAS ==> 0x40000000 + 0x400
    swd_read_word(0x40000400, &value);
    // wait bkpt halt( end of MUT main())
    if (!swd_wait_until_halted()) {
        return false;
    }

we check the RESETREAS register: it's Reset from pin-reset detected


in NRF52832 flash, use No SoftDevice, just like this code:
int main()
{
    // here do something
.........
    // important: SWD host used wait this function run finished and ok.
    __ASM volatile ("movs r0, #0"); // set R0 to 0 show success
    __ASM volatile ("bkpt  #0");   // halt MCU


    return 0;
}

when Hardware Reset happened, it should halt on bkpt instruction. when check
DBG_HCSR, it should return S_HALT flag. But read DBG_HCSR, got 0x00.

Compare STM32 MCUs, it's working fine.

What's special NRF52832 Hardware Reset Pin with SWDIO/SWCLK pins? In the document, SWJ-DP will No effect by
Hardware Reset Pin Reset behavior.
what's about core debug registers? like DHCSR, DEMCR....
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  • Hi,

    I asked one of our developers to clarify this.

    Pin reset does not reset the debug port, but it will reset the access ports and the debug logic in the ARM core. So if you look at the debug and trace overview here, then SW-DP will not be reset, but the following will be: CTRL-AP, AHB-AP, DAP bus interconnect, TPIU, and POWER.

    So what is happening in your case is that core debug is under Debug, and not SWJ-DP, so they are reset, as you can see from the table of reset behavior here. Because of this, the processor is no longer in debug mode and will therefore not stop at the breakpoint after a pin reset.

    Best regards,

    Marte

Reply
  • Hi,

    I asked one of our developers to clarify this.

    Pin reset does not reset the debug port, but it will reset the access ports and the debug logic in the ARM core. So if you look at the debug and trace overview here, then SW-DP will not be reset, but the following will be: CTRL-AP, AHB-AP, DAP bus interconnect, TPIU, and POWER.

    So what is happening in your case is that core debug is under Debug, and not SWJ-DP, so they are reset, as you can see from the table of reset behavior here. Because of this, the processor is no longer in debug mode and will therefore not stop at the breakpoint after a pin reset.

    Best regards,

    Marte

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