Current peak in system off mode

[PATA]

Hi,

I'm a beginner, and currently working to implement a low-power controller using nRF52-DK and Power Profiler Kit (PPK).

I ran the following codes (system off) and expected to see 0.3uA from the PPK as indicated in the nRF52832.

int main(void)
{
NRF_POWER->SYSTEMOFF = 1;
for(;;){}
}

However, I could observe the periodic peak current of 36uA, so I'd like to know where it comes from.

Please note that I powered cycle the boards before measuring the current to make sure to have emulated system off.

Thank you in advance.

[PATA]

I set PPK switches as follow.
- SW2 (DK)
- SW4 (Reg.)
- SW3 (DK)

For SW4, I tried both Reg. and DK, but Reg. showed lower current. 

[hmolesworth]

You may be viewing the LDO (linear Low Dropout Regulator) "skipping", over which there is no control other than to increase the reservoir capacitance; have a look at periodic-current-spikes-on-sleep for a similar discussion

[hmolesworth]

Quite so though keep in mind you can modify the frequency and hence magnitude of the current spikes by increasing or decreasing the reservoir capacitance; that does not affect average power consumption however, which is effectively fixed.

[PATA]

Thank you for clarification! 

[PATA]

Just in case, I'd like to ask if that reservoir cap means the decoupling capacitors connected to VDD. Thanks

[hmolesworth]

Yes; in general more capacitance is better though if using ceramic capacitors keep in mind derating issues where rated voltage should be double actual working voltage to avoid reduction in capacitance. Also although Tantalum performs better in that respect, leakage in tantalum capacitors (typ 3uA) usually rules them out. In a target design typically 2 x 47uF rated at 6.3 volts or 10 volts works well; more is better but then of course more board space and cost.

[PATA]

Thank you!