nrf52840 configuration and Antenna design for custom board

[Moghees]

I want to design custom board for nrf52840. I will be using configuration 5 from Reference Circuit nrf52840. I do not want to use NFC can I leave NFC pins not connected. For antenna design can I use the antenna design in nrf52840 DK?

[ketiljo]

Yes, the NCF pins can be left floating as any other GPIO not in use. 

For the RF section, you can use the DK antenna and matching network. Note how C3 is grounded.

[Moghees]

I have another question if I want to expose the SWD interface of nrf52840 and I am powering the custom board with battery what care should I take?
If you can refer me to some document that I can see for reference?

[ketiljo]

Other than general ESD protection. SWDIO has internal pullup, SWDCLK has internal pulldown. In case these aren't sufficient, it's a good ideal to at least have space for external resistors to make the design more tolerant against noise. 

[Moghees]

Thankyou

[Moghees]

I have couple of more questions:

1) We are using nrf52840 DK for developing our firmware. I want to ask do we need external debugger like Jlink debbuger ultra plus for debugging nrf52840 DK?

2) We will expose SWD interface in our custom board can you recommend device that we can use for production programing?

[ketiljo]

1. The DK comes with a debugger / programmer already https://infocenter.nordicsemi.com/topic/ug_nrf52840_dk/UG/dk/if_mcu.html

2. Take a look at this: https://infocenter.nordicsemi.com/topic/nwp_027/WP/nwp_027/intro.html

[Moghees]

Thanks for the reply so just to confirm for debugging nrf52840 DK we do not need any external debugging device. The jlink on board on DK is enough

[ketiljo]

Yes

[Moghees]

I am reading product specifications for nrf52840. In section 5.3.8.2 Regulator specifications, REG0 stage. The max current reading of 25 mA are at which voltage level of High voltage mode because high voltage mode can be from 2.5 V to 5.5 V

[ketiljo]

At any voltage level.

[Moghees]

Thanks for the help. I have another question. I was reading about GPIO current specification in product specification document. We can source/sink 15 mA current in GPIOs configured in high drive mode. We can source/sink upto 4 mA from GPIO configured in normal drive mode. If we configure GPIO in high drive mode and source current of 15 mA from it can we source 4 mA from other GPIOs that are configured in low drive mode?
What is total current we can source/sink from all GPIOs?

Regards