Chip Select for SPIM0

[Sami]

Hello,

I'm currently using SDK 17.0.2 with NRF52840. We have our SPIM3 device up and running nicely. I'm now de-risking our SPIM0 device and noticed that chip select isn't the same as in SPIM3. Can you confirm the following:

1) Is chip select handled manually with a gpio_write() call?

2) Which function do we use for SPIM0/1/2? x

nrfx_spim_xfer_dcx() or nrfx_spim_xfer()

Thank you.

[Karl Ylvisaker]

Hello,

I'm now de-risking our SPIM0 device and noticed that chip select isn't the same as in SPIM3.

What do you mean when you say that it is not the same as in SPIM3?
Are you initializing it in the same way, but it behaves differently? If so, please elaborate how it is behaving differently. Or do you mean that you would like the CS pin to be the same CS pin as the SPIM3 is using already?

1) Is chip select handled manually with a gpio_write() call?

No, if you have defined the CS pin as part of the instance's initialization the driver will take care of the CS pin handling.

The CSN pin on instances SPIM0, 1, and 2 does not support hardware control, so they must indeed be set and cleared using the GPIO functions separately. Please see my following comment for more information about this.

nrfx_spim_xfer_dcx() or nrfx_spim_xfer()

That depends if you intend to use dcx control or not. The normal SPI operation would be to use nrfx_spim_xfer.

Best regards,
Karl

[Sami]

Hi Karl, 

Elaborating a bit more: I'm seeing no activity on the CS pin of my SPIM0 instance when viewing with a logic analyzing. Upon further reading of the NRF52840 manual, page 409 states the following: "Some SPIM" instances do no support automatic control of CSN, and for those the available GPIO pins need to be used to control CSN. See Instances on page 410 for information  about what features are supported in the various SPIM instances. Looking at page 410, PSEL.CSN is not support for SPIM0. 

Here is my initialization code: 

// SPIM0, NVM, initialization:
    nrfx_spim_config_t spim0_config = NRFX_SPIM_DEFAULT_CONFIG;

    spim0_config.frequency      = NRF_SPIM_FREQ_8M;
    spim0_config.ss_pin         = E_NVM_CS_PIN;
    spim0_config.miso_pin       = E_NVM_MISO_PIN;
    spim0_config.mosi_pin       = E_NVM_MOSI_PIN;
    spim0_config.sck_pin        = E_NVM_SCLK_PIN;
    spim0_config.ss_active_high = false; // Chip select is active low.
    APP_ERROR_CHECK( nrfx_spim_init( &spim_nvm, &spim0_config, nvm_spim_event_handler, NULL ) );

So my question is, if ss_pin is correctly initialized, do I still need to call 

nrf_gpio_pin_clear(E_NVM_CS_PIN); // activate

and 

nrf_gpio_pin_set(E_NVM_CS_PIN); // deactivate

or will nrfx_spim_xfer() handle it for me? 


PSEL.CSN is set to 0xFFFFFFFF as default as it's not supported. 

[Karl Ylvisaker]

Hello again,

Oh, I am terribly sorry - my mistake. You are indeed correct that SPIM instances 0, 1, and 2 does not support hardware control of the CSN pin, as detailed in the instance description. I have edited my previous comment to highlight this. Apologies for any confusion my previous comment might have caused.

Sami said:

So my question is, if ss_pin is correctly initialized, do I still need to call 

This is correct, yes. You may also use the GPIOTE and PPI peripherals to connect the setting and clearing of the pin to an event, so that the CPU does not have to get involved every transfer. Depending on how frequent / when the transfers will happen and how timing-critical they are, this could be very beneficial.

Best regards,
Karl