SAADC VDDHDIV5 input on nRF52840 rev. 1

[Norbert]

Hello,

I got two PCA10056 1.0.0 DKs equipped with an nRF52840 rev. 1 (code AC0). Both do not measure the VCCH voltage correctly (displayed voltage ~2.4V instead of 3.0V). The setup is based on the peripheral->saadc example with the only modification being:

//      NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE(NRF_SAADC_INPUT_AIN0);
        NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE(NRF_SAADC_INPUT_VDDHDIV5);
        channel_config.gain = NRF_SAADC_GAIN1_2;

I chose to increase the input voltage swing on the ADC by configuring the gain stage from 1/6 to 1/2. This should normally give better results.

The displayed result is around 410: 410/1023 * 0.6V * 5 * 2 = 2.4V. I got the same result with the gain stage set to 1/6. The result is consistent across the two boards. Using NRF_SAADC_INPUT_VDD with gain 1/6 yields the correct result. A custom board with a rev. 2 chip works correctly with VDDHDIV5.

Can you confirm this behaviour? I did not see any erratum against explaining this. I can only guess that this behaviour (if confirmed) is a side-effect of erratum 197.

Thanks,

Norbert

[Norbert]

Hi Karl,

Karl Ylvisaker said:

Changing the gain to 1/2 will affect your input range - with this configuration you should really only be able to measure values between 0 - 1.2 V. 

VDDHDIV5 should provide 3.0V/5 = 0.6V at the input of the gain stage (ref. to PS1.5, fig. 148), so according to the PS this is fine.

Where do you see that the input range is limited to 2* 1.2V? The link you provided says the same thing as the PS, i.e. that AINx have to be between VSS and VDD (up to 3V, here). The input of the SAADC code after the gain stage should not be larger as VREF (0.6V), else the value is clipped.

Karl Ylvisaker said:

That sounds strange to me. Are you getting the same output regardless of gain stage?

The result is the measured voltage, not the raw integer value from the SAADC.So factoring in the changed gain stage, the result if the same.

Karl Ylvisaker said:

Could you share with me the code you are running when this happens?

As I said, it is the SDK 17.1.0 saadc example with the modifications in the original post (main.c, line 153). No other modifications.

Karl Ylvisaker said:

Could you try this again with the DCDC disabled, to see if it makes any difference to the values you are measuring?

To the best of my knowledge, the saadc example does not enable DCDC0. It does not make much sense on the DK as VDDH = VDD = 3.0V by the DK's HW architecture.

Karl Ylvisaker said:

Do you have any possibility of externally measuring or scoping the VDDH of the devices, such as through an oscilloscope?

Yes. VDDH is rock stable at 2.98V.

Best regards,

Norbert

[Karl Ylvisaker]

Hello again, Norbert

Thank you for your patience with this.

Norbert said:

VDDHDIV5 should provide 3.0V/5 = 0.6V at the input of the gain stage (ref. to PS1.5, fig. 148), so according to the PS this is fine.

Where do you see that the input range is limited to 2* 1.2V? The link you provided says the same thing as the PS, i.e. that AINx have to be between VSS and VDD (up to 3V, here). The input of the SAADC code after the gain stage should not be larger as VREF (0.6V), else the value is clipped.

Norbert said:

To the best of my knowledge, the saadc example does not enable DCDC0. It does not make much sense on the DK as VDDH = VDD = 3.0V by the DK's HW architecture.

Ah, yes of course, you are completely right. The DCDC is also indeed not enabled by default in the examples.
The input range will still be limited by the chosen gain and reference, but it does indeed not matter for this case since you are measuring on VDDHDIV5.

Norbert said:

Yes. VDDH is rock stable at 2.98V.

Thank you for confirming this. I assumed that you already knew, but from experience I still had to ask.

Norbert said:

The result is the measured voltage, not the raw integer value from the SAADC.So factoring in the changed gain stage, the result if the same.

Right, I was under the impression that you were talking about the raw integer value, which definitely would have been strange if it had been the case.

I do not immediately see any good explanation for this behavior.
I will try to replicate this behavior at my end tomorrow, I will update you as soon as I have got something.

Best regards,
Karl

[Norbert]

Hi Karl,

Thanks a lot for confirming.

I am very curious to see the result of your investigation. This outcome will impact our next design.

Best regards,

Norbert

[Karl Ylvisaker]

Hello again, Norbert

I just tested this on my end, and using the default SAADC init and channel config (same as the SAADC example, only changing the _AIN0 to _VDDHDIV5), I am seeing both the nRF52840 v1.0.0 and v2.0.1 output the raw integer value 170 (with a few LSB fluctuation) when powered by a steady 3 V through the VDDH.
This corresponds to ~2.98 V, which is what I would have expected..

I find it very strange that you are seeing this consistently on two different v1.0.0 boards though. Have you made any modifications to these boards? Could you also elaborate on your board configuration (switch positions) and which port you supply the 3 V on when you conducted these tests?

Best regards,
Karl

[Norbert]

Hello Karl,

Thanks for the feedback. Very strange, indeed. I just reran the experiment with the same settings you have and still get only around 136 (2.39V).

Power supply is USB. SW9 is in middle position (VDD power), the coin cell battery removed. The 3V are generated on-board from the buck regulator.

The board should be unmodified, though it is not in a pristine condition. Chip version is Q1AAC0.

I will dig further on Monday and let you know.

Thanks for your help,

Norbert

[Karl Ylvisaker]

Hello again, Norbert

Norbert said:

Power supply is USB. SW9 is in middle position (VDD power), the coin cell battery removed. The 3V are generated on-board from the buck regulator.

Oh, it seems I have misunderstood your configuration earlier.
I did my measurements with a supply of 3V directly on the VDDH input - with the SW9 switch set to Li-Po, for High Voltage mode. If the SW9 is in the VDD position the nRF52840 will enter Normal voltage mode as opposed to high-voltage mode. In normal voltage mode you should not use the VDDHDIV5 to measure your VDD bus voltage, but instead use the _VDD input directly. In your test, do you see the expected SAADC measurements if you configure the SAADC to measure _VDD instead of _VDDHDIV5 (while keeping SW9 in the VDD position)?

For all the details about the DK's power supply circuitry you could download the nRF52840 DK's schematics here, to take a closer look.
Fair warning, the power circuitry of the DK is not the easiest to familiarize with due to the array of power switches utilized for the different configurations.

Best regards,
Karl