How to enable QSPI 4-4-4 on nRF52840/SDK17.1.0

[robca]

I'm struggling to get a Micron MT25QU128ABA (https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qlhs_u_128_aba_0.pdf) in QSPI mode. I'm positive all the pins are correctly configured and can read and write to the NOR Flash using fewer data lines

If I set #define QSPI_CONFIG_READOC 4 and #define QSPI_CONFIG_WRITEOC 3 in sdk_config.h, I can write just fine, but when reading back the data, it's shifted by 2 bytes (and the initial 2 bytes are 0x88). Which seems to be a misconfiguration of the NOR FLash registers. In order to fix it, I need to set #define QSPI_CONFIG_READOC 3, and everything works, but not in 4-4-4 mode.

In order to enable 4-4-4 mode on the Micron chip, I need to set the correct bit in the volatile or non-volatile registers (different from how the NOR chip on the PCA10056 board works. But as soon as I enable the volatile register for 4-4-4, I cannot communicate with the chip anymore. It looks as if the CPU is sending commands on just one or 2 data lines and not really in 4-4-4 mode

I attached a logic analyzer [...]. EDIT: I now realize that the trace I included is not really representative (leaving it anyway for context). See next answer for more info.  Please let me know if you need a specific trace and, if so, which commands and data would help

How can I enable 4-4-4? What am I doing wrong?

[robca]

Adding more data here and a much better logic analyzer trace

I confirmed that when I program the NOR Flash to use 4-4-4, the chip expects all commands to be in sent across all the 4 data lines. The instruction nrf_drv_qspi_write(m_buffer_tx, QSPI_TEST_DATA_SIZE, 0), on the other hand, sends the command as a standard SPI command (1-x-4). So as soon as I set the right bit in the NOR register, the nRF52840 cannot communicate with the NOR flash anymore

I found a way to decode both the commands and data, and I'm enclosing a trace that shows the write enable command (0x06 and 0x38, to start programming the flash), followed by actual the address  over 4 data lines, and finally the QSPI data (starting from 00 DC, etc

So the question is: is there a way to have the nRF52840 send the QSPI commands over 4 data lines, and not just one? If not, there's no way to use Micron flash in 4-4-4 mode

For reference, here's a snippet of the Micronix datasheet, with all the supported modes for that

Here is a description of the Macronix serial flash Read modes:

• FastREAD (cmd = 0Bh): 1-1-1, Single I/O SPI Mode Read 1-1-1 = cmd on 1 channel, address on 1 channel, data on 1 channel.
• DREAD (cmd = 3Bh): 1-1-2, DSPI Mode Dual-Output Read 1-1-2 = cmd on 1 channel, address on 1 channel, data on 2 channels.
• 2READ (cmd = BBh): 1-2-2, DSPI Mode Dual-I/O Read 1-2-2 = cmd on 1 channel, address on 2 channels, data on 2 channels.
• QREAD (cmd = 6Bh): 1-1-4, QSPI Mode Quad-Output Read 1-1-4 = cmd on 1 channel, address on 1 channel, data on 4 channels
• 4READ (cmd = EBh): 1-4-4, QSPI Mode Quad-I/O Read 1-4-4 = cmd on 1 channel, address on 4 channels, data on 4 channels.
• In QPI mode, the command is received by the flash in 4 parallel channels as well. 4READ (cmd = EBh): 4-4-4, QPI Read 4-4-4 = cmd on 4 channels, address on 4 channels, data on 4 channels.

Could you please provide a definition of the correspondence between the various settings of QSPI_CONFIG_READOC and QSPI_CONFIG_WRITEOC, and the standard QSPI  x-y-z format? It would really help me in understanding what is happening. I could not find this information in any of the Nordic documentation

[ovrebekk]

Hi 

Have you checked the Interface Description chapter in the product specification?
It shows exactly what is clocked out on the different lines depending on which write/read/erase operation you are using. 

To see which operations are mapped to which READOC/WRITEOC values, please have a look at the IFCONFIG0 register description.

Could you try to set READOC to 3 and WRITEOC to 2 and see if it works better?

Thanks for sharing the datasheet for your sensor. Looking at the description of the QUAD OUTPUT FAST READ - 6Bh operation, as an example, it looks like it should be compatible with the nRF device when using the READ4O operation:

Diagram from the nRF52840 PS for comparison:

When you say the command should be sent over 4 lines, you really mean that the first 8 byte command should be sent on all data lines?

Looking at the Micron datasheet it doesn't look like this is the case. After all, until the command is read the device wouldn't know whether to use 1, 2 or 4 data lines. 

Best regards
Torbjørn

[robca]

I did look at the Interface Description, but what I originally missed is the mapping to the various settings described in the IFCONFIG0. Thanks for that explicit link, my bad for missing it originally

ovrebekk said:

When you say the command should be sent over 4 lines, you really mean that the first 8 byte command should be sent on all data lines?

Yes. that is exactly what the first 4 in 4-4-4 (4 command, 4 address, 4 data) means. The figure 25 in your answers shows that quad mode uses all 4 lines for the command as well as opposed to the extended mode (1-1-4), that shows the command and address on one line, and data on 4

Here's an even clearer description from the Macronix datasheet

From what I can see from the logic analyzer traces, Nordic only supports 1-1-4 and 1-4-4 modes, not 4-4-4. That means I cannot put the Micron NOR flash into quad mode in the register, since once that bit is set, the flash only accepts 4-4-4 (other flash chips accept both, like Macronix, as you can see here https://www.macronix.com/Lists/ApplicationNote/Attachments/1899/AN0251V1%20-%20Macronix%20Serial%20Flash%20Multi%20IO%20Introduction.pdf and copied below)

I can talk to the Micron chip using either 1-1-4 or 1-4-4. If you confirm that there is no 4-4-4 available, I'll run a few more tests and see which of the combinations is th eone that works best in terms of speed and reliability

[ovrebekk]

Hi 

I can confirm that there is no 4-4-4 mode available, yes. You would have to use the 1-1-4 or 1-4-4 instructions. 

For the nRF5340 we introduced some improvements to the QSPI peripheral, including support for higher clock speeds, but there is still no support for the 4-4-4 instructions. 

Unless you send very short read/write instructions the difference between sending the command byte in 2 or 8 cycles should be very modest. 

Best regards
Torbjørn

[robca]

Thanks for the confirmation. Yes, unless I make a lot of single cell requests, the performance impact is rather limited.

I noticed that using #define QSPI_CONFIG_READOC 4 there are problems and the nRD52840 receives two extra 0x88 from the Micron flash before the actual data, so the only way to make it work reliably is to use #define QSPI_CONFIG_READOC 3 and use 1-1-4. It looks like a timing problems, and I might have to look into this further in case we need to use 1-4-4. For now, 1-1-4 will have to do. I'm adding this here in case anyone in the future happens to see the 0x88 data (searching on the internet I found a few mentions of 0x88 and Micron, but none of those threads provided a final answer)

[ovrebekk]

Hi 

Thanks for sharing your findings. The difference between 1-1-4 and 1-4-4 is larger than the difference between 1-4-4 and 4-4-4, but again the difference is not very large if you use longer transactions. 

Alternatively you could just ignore the 0x88 bytes in software, but this won't work if you plan to use XIP. 

Best regards
Torbjørn