Minimum Pulse-Width Resolution for nRF52840 PWM Module

[johnwest]

Hello All,

What is the minimum pulse width resolution for the nRF52840's PWM module?

Thanks,
johnwest

[haakonsh]

I'm not quite sure what exactly you are asking for, so I'll just list the relevant timing specs:

• 16MHz base clock
• 1x - 128x PRESCALER (16MHz - 125kHz)
• 15-bit COUNTERTOP value (3 - 32767)
• 15-bit compare values (1 - 32767)

Full specs: PWM — Pulse width modulation 

[johnwest]

haakonsh,

So, is the minimum pulse width 1uS?  1nS?  1pS?  

Thanks,
johnwest

[hmolesworth]

16MHz clock gives 62.5 nSec minimum pulse width.

[johnwest]

So, min pulse width is 1 / (base clock) - is that in the spec someplace?

[hmolesworth]

No idea, but with a x1 divider each step is 1/16MHz; the 16MHz is fixed in stone (well, silicon), no way of changing that. To get 8MHz PWM at least 4 steps are required 0-1-0-1 as period (COUNTERTOP) cannot be less than 3. A COUNTERTOP value of 4 with the sequence 0-1-0-1 gives 8MHz PWM signal.

[johnwest]

hmolesworth,

OK - so 125 nS then,

Thanks,
John

[hmolesworth]

Welcome, but 125nSec period or 62.5nSec pulsewidth :-)

[johnwest]

@hmolesworth,

Sure - assuming a 50% PDC (positive duty cycle) if the GPIO hardware allows this and indeed the minimum period is defined as 1 / (base clock) - still would be nice to see this called out in detail in the specs.

Thanks,
John