Sure - assuming a 50% PDC (positive duty cycle) if the GPIO hardware allows this and indeed the minimum period is defined as 1 / (base clock) - still would be nice to see this called out in detail in the specs.
According to the nRF52840 Errata list, at 400Khz operation, the clock is at 1.25 usec. But this is too short and violates the spec of 1.3 usec. Only workaround is to slow the frequency to 390Khz, but this means the standard macros in the SDK cannot be used.
Don't forget about sensing the SDA line to see if it is stuck low. If it is, you have to clock the I2C until it is no longer stuck (1 to 9 clocks). So, GPIO to sense line, then enable and cfg TWIM, and the use the bus. This must be done for every transfer.
