NRF52840 QSPI IFTIMING Problem

[Bing]

Dear,

We are working on our custom boards to develop a watch product which need external flash memory connected by QSPI interface. In this product, the UI images and font bitmaps store in the external memory. We found the screen of some watch samples display noise content(the data source comes from the external flash memory).  We tried to change IFTIMING register value, and we found the problem watches display problem been fixed. But some other watches no need to change the default value of IFTIMING (the default whole register value 0x00000200). The proportion of problem products is about 6%. 

We want to know why the problem products can fix this issue by change IFTIMING register while some most of the product (the other 96%) no need to change this register. And whether the IFTIMING register change would lead other unknown issues.

The following is my understanding about IFTIMING, seems the default value is not fit the the CLOCK mode=0 (CPOL=0, CPHA=0) with the QSPI clock=32MHz.

Our the external flash memory is XT25F128BWOIGT.

[haakonsh]

We want to know why the problem products can fix this issue by change IFTIMING register while some most of the product (the other 96%) no need to change this register. And whether the IFTIMING register change would lead other unknown issues.

I don't know why you see this issue exactly. I suggest we do a HW review to see if there is any obvious signal integrity issues in the design. 
We don't know if changing the timings will lead to unknow problems in your design. 

If you change the IFTIMING of the 'good' devices, does it have a negative impact, or do they continue to function as intended?

[you can123]

We tested a batch of machines after changing IFTIMING, and did not find any adverse effects on the use, or it may be that our testing time is relatively short. But this QSPI, we are directly connected to the MCU, there are no additional devices in between , But I did not use the pins recommended by NORDIC, we used the QSPI pins as follows:

//flash	
#define GPIO_FLASH_MOSI				GPIO1_10	//IO0
#define GPIO_FLASH_MISO				GPIO1_14	//IO1
#define GPIO_FLASH_SCLK				GPIO1_11
#define GPIO_FLASH_CS				GPIO1_15
	
#define GPIO_FLASH_WP				GPIO1_13	//IO2
#define GPIO_FLASH_HOLD				GPIO1_12	//IO3