PRECISERR due to the address violation at 0x40009500 (BFAR) cause hardfault for NRF9160ns

[ismail_embedded]

I have a legacy code base  for NRF9160 with a custom board folder which created manually by applying installing manually steps in the past. I have neither experience with Nordic ecosystem nor Zephyr before.

Codebase is building successfully however it falls hard fault whenever I attempted to run zephyr.elf file via OZONE.

Ozone says there is PRECISERR and BFAR = 0x4000 9500.

Software are using uarte and this adress could be related with this. On the other hand, an instruction on my hand says " before the build, you should copy custom uarte.c driver to zephyr/driver/serial/uarte" I do not know why.

Here is the code snippet. 

As far as I reviewed. This address is belongs to the uarte enable register. The project are using uart0 and uart1. I do not know which prj.conf I need to share with you please navigate me.

/*
 * Copyright (c) 2018 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @brief Driver for Nordic Semiconductor nRF UARTE
 */

#include <drivers/uart.h>
#include <hal/nrf_gpio.h>
#include <hal/nrf_uarte.h>
#include <nrfx_timer.h>
#include <sys/util.h>
#include <kernel.h>
#include <logging/log.h>
#include <helpers/nrfx_gppi.h>
LOG_MODULE_REGISTER(uart_nrfx_uarte, LOG_LEVEL_ERR);

/* Generalize PPI or DPPI channel management */
#if defined(CONFIG_HAS_HW_NRF_PPI)
#include <nrfx_ppi.h>
#define gppi_channel_t nrf_ppi_channel_t
#define gppi_channel_alloc nrfx_ppi_channel_alloc
#define gppi_channel_enable nrfx_ppi_channel_enable
#elif defined(CONFIG_HAS_HW_NRF_DPPIC)
#include <nrfx_dppi.h>
#define gppi_channel_t uint8_t
#define gppi_channel_alloc nrfx_dppi_channel_alloc
#define gppi_channel_enable nrfx_dppi_channel_enable
#else
#error "No PPI or DPPI"
#endif


#if (defined(CONFIG_UART_0_NRF_UARTE) &&         \
     defined(CONFIG_UART_0_INTERRUPT_DRIVEN)) || \
    (defined(CONFIG_UART_1_NRF_UARTE) &&         \
     defined(CONFIG_UART_1_INTERRUPT_DRIVEN)) || \
    (defined(CONFIG_UART_2_NRF_UARTE) &&         \
     defined(CONFIG_UART_2_INTERRUPT_DRIVEN)) || \
    (defined(CONFIG_UART_3_NRF_UARTE) &&         \
     defined(CONFIG_UART_3_INTERRUPT_DRIVEN))
	#define UARTE_INTERRUPT_DRIVEN	1
#endif

#if	(defined(CONFIG_UART_0_NRF_UARTE) && !defined(CONFIG_UART_0_ASYNC)) || \
	(defined(CONFIG_UART_1_NRF_UARTE) && !defined(CONFIG_UART_1_ASYNC)) || \
	(defined(CONFIG_UART_2_NRF_UARTE) && !defined(CONFIG_UART_2_ASYNC)) || \
	(defined(CONFIG_UART_3_NRF_UARTE) && !defined(CONFIG_UART_3_ASYNC))
#define UARTE_ANY_NONE_ASYNC 1
#endif

uint32_t uarte_prev_rx_amount;
uint8_t uarte_prev_dirty;
uint8_t po_flush_buf[5];

/*
 * RX timeout is divided into time slabs, this define tells how many divisions
 * should be made. More divisions - higher timeout accuracy and processor usage.
 */
#define RX_TIMEOUT_DIV 5

#ifdef CONFIG_UART_ASYNC_API
struct uarte_async_cb {
	uart_callback_t user_callback;
	void *user_data;

	const uint8_t *tx_buf;
	volatile size_t tx_size;
	uint8_t *pend_tx_buf;

	struct k_timer tx_timeout_timer;

	uint8_t *rx_buf;
	size_t rx_buf_len;
	size_t rx_offset;
	uint8_t *rx_next_buf;
	size_t rx_next_buf_len;
	uint32_t rx_total_byte_cnt; /* Total number of bytes received */
	uint32_t rx_total_user_byte_cnt; /* Total number of bytes passed to user */
	int32_t rx_timeout; /* Timeout set by user */
	int32_t rx_timeout_slab; /* rx_timeout divided by RX_TIMEOUT_DIV */
	int32_t rx_timeout_left; /* Current time left until user callback */
	struct k_timer rx_timeout_timer;
	union {
		gppi_channel_t ppi;
		uint32_t cnt;
	} rx_cnt;
	volatile int tx_amount;

	bool rx_enabled;
	bool hw_rx_counting;
	/* Flag to ensure that RX timeout won't be executed during ENDRX ISR */
	volatile bool is_in_irq;
};
#endif

#ifdef UARTE_INTERRUPT_DRIVEN
struct uarte_nrfx_int_driven {
	uart_irq_callback_user_data_t cb; /**< Callback function pointer */
	void *cb_data; /**< Callback function arg */
	uint8_t *tx_buffer;
	uint16_t tx_buff_size;
	volatile bool disable_tx_irq;
#ifdef CONFIG_PM_DEVICE
	bool rx_irq_enabled;
#endif
	atomic_t fifo_fill_lock;
};
#endif

/* Device data structure */
struct uarte_nrfx_data {
	const struct device *dev;
	struct uart_config uart_config;
#ifdef UARTE_INTERRUPT_DRIVEN
	struct uarte_nrfx_int_driven *int_driven;
#endif
#ifdef CONFIG_UART_ASYNC_API
	struct uarte_async_cb *async;
#endif
	atomic_val_t poll_out_lock;
#ifdef CONFIG_PM_DEVICE
	uint32_t pm_state;
#endif
	uint8_t char_out;
	uint8_t rx_data;
	gppi_channel_t ppi_ch_endtx;
};

#define CTS_PIN_SET_MASK BIT(1)
#define RTS_PIN_SET_MASK BIT(2)

#define IS_CTS_PIN_SET(mask) (mask & CTS_PIN_SET_MASK)
#define IS_RTS_PIN_SET(mask) (mask & RTS_PIN_SET_MASK)

/**
 * @brief Structure for UARTE configuration.
 */
struct uarte_nrfx_config {
	NRF_UARTE_Type *uarte_regs; /* Instance address */
	uint8_t rts_cts_pins_set;
	bool gpio_mgmt;
	bool ppi_endtx;
#ifdef CONFIG_UART_ASYNC_API
	nrfx_timer_t timer;
#endif
};

struct uarte_init_config {
	uint32_t  pseltxd; /* PSEL.TXD register value */
	uint32_t  pselrxd; /* PSEL.RXD register value */
	uint32_t  pselcts; /* PSEL.CTS register value */
	uint32_t  pselrts; /* PSEL.RTS register value */
};

static inline struct uarte_nrfx_data *get_dev_data(const struct device *dev)
{
	return dev->data;
}

static inline const struct uarte_nrfx_config *get_dev_config(const struct device *dev)
{
	return dev->config;
}

static inline NRF_UARTE_Type *get_uarte_instance(const struct device *dev)
{
	const struct uarte_nrfx_config *config = get_dev_config(dev);

	return config->uarte_regs;
}

static void endtx_isr(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	int key = irq_lock();

	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDTX);
		nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPTX);
	}

	irq_unlock(key);

}

#ifdef UARTE_ANY_NONE_ASYNC
/**
 * @brief Interrupt service routine.
 *
 * This simply calls the callback function, if one exists.
 *
 * @param arg Argument to ISR.
 *
 * @return N/A
 */
static void uarte_nrfx_isr_int(void *arg)
{
	const struct device *dev = arg;
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	/* If interrupt driven and asynchronous APIs are disabled then UART
	 * interrupt is still called to stop TX. Unless it is done using PPI.
	 */
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
		nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
		endtx_isr(dev);
	}

#ifdef UARTE_INTERRUPT_DRIVEN
	struct uarte_nrfx_data *data = get_dev_data(dev);

	if (!data->int_driven) {
		return;
	}

	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
		data->int_driven->fifo_fill_lock = 0;
		if (data->int_driven->disable_tx_irq) {
			nrf_uarte_int_disable(uarte,
					      NRF_UARTE_INT_TXSTOPPED_MASK);
			data->int_driven->disable_tx_irq = false;
			return;
		}

	}


	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ERROR)) {
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ERROR);
	}

	if (data->int_driven->cb) {
		data->int_driven->cb(dev, data->int_driven->cb_data);
	}
#endif /* UARTE_INTERRUPT_DRIVEN */
}
#endif /* UARTE_ANY_NONE_ASYNC */

/**
 * @brief Set the baud rate
 *
 * This routine set the given baud rate for the UARTE.
 *
 * @param dev UARTE device struct
 * @param baudrate Baud rate
 *
 * @return 0 on success or error code
 */
static int baudrate_set(const struct device *dev, uint32_t baudrate)
{
	nrf_uarte_baudrate_t nrf_baudrate; /* calculated baudrate divisor */
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	switch (baudrate) {
	case 300:
		/* value not supported by Nordic HAL */
		nrf_baudrate = 0x00014000;
		break;
	case 600:
		/* value not supported by Nordic HAL */
		nrf_baudrate = 0x00027000;
		break;
	case 1200:
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
		break;
	case 2400:
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
		break;
	case 4800:
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
		break;
	case 9600:
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
		break;
	case 14400:
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
		break;
	case 19200:
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
		break;
	case 28800:
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
		break;
	case 31250:
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
		break;
	case 38400:
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
		break;
	case 56000:
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
		break;
	case 57600:
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
		break;
	case 76800:
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
		break;
	case 115200:
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
		break;
	case 230400:
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
		break;
	case 250000:
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
		break;
	case 460800:
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
		break;
	case 921600:
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
		break;
	case 1000000:
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
		break;
	default:
		return -EINVAL;
	}

	nrf_uarte_baudrate_set(uarte, nrf_baudrate);

	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
	nrf_uarte_config_t uarte_cfg;

#if defined(UARTE_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
	case UART_CFG_STOP_BITS_1:
		uarte_cfg.stop = NRF_UARTE_STOP_ONE;
		break;
	case UART_CFG_STOP_BITS_2:
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
		break;
	default:
		return -ENOTSUP;
	}
#else
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
	case UART_CFG_FLOW_CTRL_NONE:
		uarte_cfg.hwfc = NRF_UARTE_HWFC_DISABLED;
		break;
	case UART_CFG_FLOW_CTRL_RTS_CTS:
		if (get_dev_config(dev)->rts_cts_pins_set) {
			uarte_cfg.hwfc = NRF_UARTE_HWFC_ENABLED;
		} else {
			return -ENOTSUP;
		}
		break;
	default:
		return -ENOTSUP;
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
	case UART_CFG_PARITY_NONE:
		uarte_cfg.parity = NRF_UARTE_PARITY_EXCLUDED;
		break;
	case UART_CFG_PARITY_EVEN:
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
		break;
#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	case UART_CFG_PARITY_ODD:
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
		uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_ODD;
		break;
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	get_dev_data(dev)->uart_config = *cfg;

	return 0;
}

static int uarte_nrfx_config_get(const struct device *dev,
				 struct uart_config *cfg)
{
	*cfg = get_dev_data(dev)->uart_config;
	return 0;
}


static int uarte_nrfx_err_check(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	/* register bitfields maps to the defines in uart.h */
	return nrf_uarte_errorsrc_get_and_clear(uarte);
}

/* Function returns true if new transfer can be started. Since TXSTOPPED
 * (and ENDTX) is cleared before triggering new transfer, TX is ready for new
 * transfer if any event is set.
 */
static bool is_tx_ready(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	bool ppi_endtx = get_dev_config(dev)->ppi_endtx;

	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
		(!ppi_endtx ?
		       nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX) : 0);
}

/* Wait until the transmitter is in the idle state. When this function returns,
 * IRQ's are locked with the returned key.
 */
static int wait_tx_ready(const struct device *dev)
{
	int key;

	do {
		/* wait arbitrary time before back off. */
		bool res;

		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);

		if (res) {
			key = irq_lock();
			if (is_tx_ready(dev)) {
				break;
			}

			irq_unlock(key);
		}
		k_msleep(1);
	} while (1);

	return key;
}

static void tx_start(NRF_UARTE_Type *uarte, const uint8_t *buf, size_t len)
{
	nrf_uarte_tx_buffer_set(uarte, buf, len);
	nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDTX);
	nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_TXSTOPPED);
	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTTX);
}

#ifdef CONFIG_UART_ASYNC_API

static inline bool hw_rx_counting_enabled(struct uarte_nrfx_data *data)
{
	if (IS_ENABLED(CONFIG_UARTE_NRF_HW_ASYNC)) {
		return data->async->hw_rx_counting;
	} else {
		return false;
	}
}

static void timer_handler(nrf_timer_event_t event_type, void *p_context) { }
static void rx_timeout(struct k_timer *timer);
static void tx_timeout(struct k_timer *timer);

static int uarte_nrfx_rx_counting_init(const struct device *dev)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	const struct uarte_nrfx_config *cfg = get_dev_config(dev);
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	int ret;

	if (hw_rx_counting_enabled(data)) {
		nrfx_timer_config_t tmr_config = NRFX_TIMER_DEFAULT_CONFIG;

		tmr_config.mode = NRF_TIMER_MODE_COUNTER;
		tmr_config.bit_width = NRF_TIMER_BIT_WIDTH_32;
		ret = nrfx_timer_init(&cfg->timer,
				      &tmr_config,
				      timer_handler);
		if (ret != NRFX_SUCCESS) {
			LOG_ERR("Timer already initialized, "
				"switching to software byte counting.");
			data->async->hw_rx_counting = false;
		} else {
			nrfx_timer_enable(&cfg->timer);
			nrfx_timer_clear(&cfg->timer);
		}
	}

	if (hw_rx_counting_enabled(data)) {
		ret = gppi_channel_alloc(&data->async->rx_cnt.ppi);
		if (ret != NRFX_SUCCESS) {
			LOG_ERR("Failed to allocate PPI Channel, "
				"switching to software byte counting.");
			data->async->hw_rx_counting = false;
			nrfx_timer_uninit(&cfg->timer);
		}
	}

	if (hw_rx_counting_enabled(data)) {
#if CONFIG_HAS_HW_NRF_PPI
		ret = nrfx_ppi_channel_assign(
			data->async->rx_cnt.ppi,
			nrf_uarte_event_address_get(uarte,
						    NRF_UARTE_EVENT_RXDRDY),
			nrfx_timer_task_address_get(&cfg->timer,
						    NRF_TIMER_TASK_COUNT));

		if (ret != NRFX_SUCCESS) {
			return -EIO;
		}
#else
		nrf_uarte_publish_set(uarte,
				      NRF_UARTE_EVENT_RXDRDY,
				      data->async->rx_cnt.ppi);
		nrf_timer_subscribe_set(cfg->timer.p_reg,
					NRF_TIMER_TASK_COUNT,
					data->async->rx_cnt.ppi);

#endif
		ret = gppi_channel_enable(data->async->rx_cnt.ppi);
		if (ret != NRFX_SUCCESS) {
			return -EIO;
		}
	} else {
		nrf_uarte_int_enable(uarte, NRF_UARTE_INT_RXDRDY_MASK);
	}

	return 0;
}

static int uarte_nrfx_init(const struct device *dev)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	int ret = uarte_nrfx_rx_counting_init(dev);

	if (ret != 0) {
		return ret;
	}
	nrf_uarte_int_enable(uarte,
			     NRF_UARTE_INT_ENDRX_MASK |
			     NRF_UARTE_INT_RXSTARTED_MASK |
			     NRF_UARTE_INT_ERROR_MASK |
			     NRF_UARTE_INT_RXTO_MASK);
	nrf_uarte_enable(uarte);

	/**
	 * Stop any currently running RX operations. This can occur when a
	 * bootloader sets up the UART hardware and does not clean it up
	 * before jumping to the next application.
	 */
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXSTARTED)) {
		nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPRX);
		while (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXTO)) {
			/* Busy wait for event to register */
		}
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXSTARTED);
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXTO);
	}

	k_timer_init(&data->async->rx_timeout_timer, rx_timeout, NULL);
	k_timer_user_data_set(&data->async->rx_timeout_timer, data);
	k_timer_init(&data->async->tx_timeout_timer, tx_timeout, NULL);
	k_timer_user_data_set(&data->async->tx_timeout_timer, data);

	return 0;
}

static int uarte_nrfx_tx(const struct device *dev, const uint8_t *buf,
			 size_t len,
			 int32_t timeout)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	if (!nrfx_is_in_ram(buf)) {
		return -ENOTSUP;
	}

	int key = irq_lock();

	if (data->async->tx_size) {
		irq_unlock(key);
		return -EBUSY;
	} else {
		data->async->tx_size = len;
	}

	nrf_uarte_int_enable(uarte, NRF_UARTE_INT_TXSTOPPED_MASK);

	if (!is_tx_ready(dev)) {
		/* Active poll out, postpone until it is completed. */
		data->async->pend_tx_buf = (uint8_t *)buf;
	} else {
		data->async->tx_buf = buf;
		data->async->tx_amount = -1;
		tx_start(uarte, buf, len);
	}

	irq_unlock(key);

	if (data->uart_config.flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS
	    && timeout != SYS_FOREVER_MS) {
		k_timer_start(&data->async->tx_timeout_timer, K_MSEC(timeout),
			      K_NO_WAIT);
	}
	return 0;
}

static int uarte_nrfx_tx_abort(const struct device *dev)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	if (data->async->tx_buf == NULL) {
		return -EFAULT;
	}
	k_timer_stop(&data->async->tx_timeout_timer);
	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPTX);

	return 0;
}

static int uarte_nrfx_rx_enable(const struct device *dev, uint8_t *buf,
				size_t len,
				int32_t timeout)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	if (nrf_uarte_rx_pin_get(uarte) == NRF_UARTE_PSEL_DISCONNECTED) {
		__ASSERT(false, "TX only UARTE instance");
		return -ENOTSUP;
	}

	data->async->rx_timeout = timeout;
	data->async->rx_timeout_slab =
		MAX(timeout / RX_TIMEOUT_DIV,
		    NRFX_CEIL_DIV(1000, CONFIG_SYS_CLOCK_TICKS_PER_SEC));

	data->async->rx_buf = buf;
	data->async->rx_buf_len = len;
	data->async->rx_offset = 0;
	data->async->rx_next_buf = NULL;
	data->async->rx_next_buf_len = 0;
	nrf_uarte_rx_buffer_set(uarte, buf, len);

	nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
	nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXSTARTED);

	data->async->rx_enabled = true;
	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);
	return 0;
}

static int uarte_nrfx_rx_buf_rsp(const struct device *dev, uint8_t *buf,
				 size_t len)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	int err;
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	int key = irq_lock();

	if ((data->async->rx_buf == NULL)) {
		err = -EACCES;
	} else if (data->async->rx_next_buf == NULL) {
		data->async->rx_next_buf = buf;
		data->async->rx_next_buf_len = len;
		nrf_uarte_rx_buffer_set(uarte, buf, len);
		nrf_uarte_shorts_enable(uarte, NRF_UARTE_SHORT_ENDRX_STARTRX);
		err = 0;
	} else {
		err = -EBUSY;
	}

	irq_unlock(key);

	return err;
}

static int uarte_nrfx_callback_set(const struct device *dev,
				   uart_callback_t callback,
				   void *user_data)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);

	data->async->user_callback = callback;
	data->async->user_data = user_data;

	return 0;
}

static int uarte_nrfx_rx_disable(const struct device *dev)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	if (data->async->rx_buf == NULL) {
		return -EFAULT;
	}
	if (data->async->rx_next_buf != NULL) {
		nrf_uarte_shorts_disable(uarte, NRF_UARTE_SHORT_ENDRX_STARTRX);
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXSTARTED);
	}

	k_timer_stop(&data->async->rx_timeout_timer);
	data->async->rx_enabled = false;

	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPRX);

	return 0;
}

static void tx_timeout(struct k_timer *timer)
{
	struct uarte_nrfx_data *data = k_timer_user_data_get(timer);
	(void) uarte_nrfx_tx_abort(data->dev);
}

static void user_callback(const struct device *dev, struct uart_event *evt)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);

	if (data->async->user_callback) {
		data->async->user_callback(dev, evt, data->async->user_data);
	}
}

/**
 * Whole timeout is divided by RX_TIMEOUT_DIV into smaller units, rx_timeout
 * is executed periodically every rx_timeout_slab ms. If between executions
 * data was received, then we start counting down time from start, if not, then
 * we subtract rx_timeout_slab from rx_timeout_left.
 * If rx_timeout_left is less than rx_timeout_slab it means that receiving has
 * timed out and we should tell user about that.
 */
static void rx_timeout(struct k_timer *timer)
{
	struct uarte_nrfx_data *data = k_timer_user_data_get(timer);
	const struct device *dev = data->dev;
	const struct uarte_nrfx_config *cfg = get_dev_config(dev);
	uint32_t read;

	if (data->async->is_in_irq) {
		return;
	}

	/* Disable ENDRX ISR, in case ENDRX event is generated, it will be
	 * handled after rx_timeout routine is complete.
	 */
	nrf_uarte_int_disable(get_uarte_instance(dev),
			      NRF_UARTE_INT_ENDRX_MASK);

	if (hw_rx_counting_enabled(data)) {
		read = nrfx_timer_capture(&cfg->timer, 0);
	} else {
		read = data->async->rx_cnt.cnt;
	}

	/* Check if data was received since last function call */
	if (read != data->async->rx_total_byte_cnt) {
		data->async->rx_total_byte_cnt = read;
		data->async->rx_timeout_left = data->async->rx_timeout;
	}

	/* Check if there is data that was not sent to user yet
	 * Note though that 'len' is a count of data bytes received, but not
	 * necessarily the amount available in the current buffer
	 */
	int32_t len = data->async->rx_total_byte_cnt
		    - data->async->rx_total_user_byte_cnt;

	/* Check for current buffer being full.
	 * if the UART receives characters before the the ENDRX is handled
	 * and the 'next' buffer is set up, then the SHORT between ENDRX and
	 * STARTRX will mean that data will be going into to the 'next' buffer
	 * until the ENDRX event gets a chance to be handled.
	 */
	bool clipped = false;

	if (len + data->async->rx_offset > data->async->rx_buf_len) {
		len = data->async->rx_buf_len - data->async->rx_offset;
		clipped = true;
	}

	if (len > 0) {
		if (clipped ||
			(data->async->rx_timeout_left
				< data->async->rx_timeout_slab)) {
			/* rx_timeout ms elapsed since last receiving */
			struct uart_event evt = {
				.type = UART_RX_RDY,
				.data.rx.buf = data->async->rx_buf,
				.data.rx.len = len,
				.data.rx.offset = data->async->rx_offset
			};
			data->async->rx_offset += len;
			data->async->rx_total_user_byte_cnt += len;
			user_callback(dev, &evt);
		} else {
			data->async->rx_timeout_left -=
				data->async->rx_timeout_slab;
		}

		/* If theres nothing left to report until the buffers are
		 * switched then the timer can be stopped
		 */
		if (clipped) {
			k_timer_stop(&data->async->rx_timeout_timer);
		}
	}

	nrf_uarte_int_enable(get_uarte_instance(dev),
			     NRF_UARTE_INT_ENDRX_MASK);
}

#define UARTE_ERROR_FROM_MASK(mask)					\
	((mask) & NRF_UARTE_ERROR_OVERRUN_MASK ? UART_ERROR_OVERRUN	\
	 : (mask) & NRF_UARTE_ERROR_PARITY_MASK ? UART_ERROR_PARITY	\
	 : (mask) & NRF_UARTE_ERROR_FRAMING_MASK ? UART_ERROR_FRAMING	\
	 : (mask) & NRF_UARTE_ERROR_BREAK_MASK ? UART_BREAK		\
	 : 0)

static void error_isr(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	uint32_t err = nrf_uarte_errorsrc_get_and_clear(uarte);
	struct uart_event evt = {
		.type = UART_RX_STOPPED,
		.data.rx_stop.reason = UARTE_ERROR_FROM_MASK(err),
	};
	user_callback(dev, &evt);
	(void) uarte_nrfx_rx_disable(dev);
}

static void rxstarted_isr(const struct device *dev)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	struct uart_event evt = {
		.type = UART_RX_BUF_REQUEST,
	};
	user_callback(dev, &evt);
	if (data->async->rx_timeout != SYS_FOREVER_MS) {
		data->async->rx_timeout_left = data->async->rx_timeout;
		k_timer_start(&data->async->rx_timeout_timer,
			      K_MSEC(data->async->rx_timeout_slab),
			      K_MSEC(data->async->rx_timeout_slab));
	}
}

static void endrx_isr(const struct device *dev)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	if (!data->async->rx_enabled) {
		if (data->async->rx_buf == NULL) {
			/* This condition can occur only after triggering
			 * FLUSHRX task.
			 */
			const int rx_amount = nrf_uarte_rx_amount_get(uarte);
			int real_rx_amount = 0;
			if(rx_amount != uarte_prev_rx_amount) {
				real_rx_amount = rx_amount;
			} else {
				for(int i = 0; i < sizeof(po_flush_buf); i++) {
					if(po_flush_buf[i] != uarte_prev_dirty) {
						real_rx_amount = rx_amount;
						break;
					}
				}
			}
			struct uart_event evt = {
				.type = UART_RX_DISABLED,
				.data.rx.buf = &po_flush_buf,
				.data.rx.len = real_rx_amount,
				.data.rx.offset = -1,
			};
			user_callback(dev, &evt);
			return;
		}
	}

	data->async->is_in_irq = true;

	/* ensure rx timer is stopped - it will be restarted in RXSTARTED
	 * handler if needed
	 */
	k_timer_stop(&data->async->rx_timeout_timer);

	/* this is the amount that the EasyDMA controller has copied into the
	 * buffer
	 */
	const int rx_amount = nrf_uarte_rx_amount_get(uarte);

	/* The 'rx_offset' can be bigger than 'rx_amount', so it the length
	 * of data we report back the the user may need to be clipped.
	 * This can happen because the 'rx_offset' count derives from RXRDY
	 * events, which can occur already for the next buffer before we are
	 * here to handle this buffer. (The next buffer is now already active
	 * because of the ENDRX_STARTRX shortcut)
	 */
	int rx_len = rx_amount - data->async->rx_offset;

	if (rx_len < 0) {
		rx_len = 0;
	}

	data->async->rx_total_user_byte_cnt += rx_len;

	if (!hw_rx_counting_enabled(data)) {
		/* Prevent too low value of rx_cnt.cnt which may occur due to
		 * latencies in handling of the RXRDY interrupt. Because whole
		 * buffer was filled we can be sure that rx_total_user_byte_cnt
		 * is current total number of received bytes.
		 */
		data->async->rx_cnt.cnt = data->async->rx_total_user_byte_cnt;
	}

	/* Only send the RX_RDY event if there is something to send */
	if (rx_len > 0) {
		struct uart_event evt = {
			.type = UART_RX_RDY,
			.data.rx.buf = data->async->rx_buf,
			.data.rx.len = rx_len,
			.data.rx.offset = data->async->rx_offset,
		};
		user_callback(dev, &evt);
	}

	if (!data->async->rx_enabled) {
		data->async->is_in_irq = false;
		return;
	}

	struct uart_event evt = {
		.type = UART_RX_BUF_RELEASED,
		.data.rx_buf.buf = data->async->rx_buf,
	};
	user_callback(dev, &evt);

	/* If there is a next buffer, then STARTRX will have already been
	 * invoked by the short (the next buffer will be filling up already)
	 * and here we just do the swap of which buffer the driver is following,
	 * the next rx_timeout() will update the rx_offset.
	 */
	int key = irq_lock();

	if (data->async->rx_next_buf) {
		data->async->rx_buf = data->async->rx_next_buf;
		data->async->rx_buf_len = data->async->rx_next_buf_len;
		data->async->rx_next_buf = NULL;
		data->async->rx_next_buf_len = 0;

		data->async->rx_offset = 0;
		/* Check is based on assumption that ISR handler handles
		 * ENDRX before RXSTARTED so if short was set on time, RXSTARTED
		 * event will be set.
		 */
		if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXSTARTED)) {
			nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);
		}
		/* Remove the short until the subsequent next buffer is setup */
		nrf_uarte_shorts_disable(uarte, NRF_UARTE_SHORT_ENDRX_STARTRX);
	} else {
		data->async->rx_buf = NULL;
	}

	irq_unlock(key);

	if (data->async->rx_buf == NULL) {
		evt.type = UART_RX_DISABLED;
		user_callback(dev, &evt);
	}

	data->async->is_in_irq = false;
}

/* This handler is called when the reception is interrupted, in contrary to
 * finishing the reception after filling all provided buffers, in which case
 * the events UART_RX_BUF_RELEASED and UART_RX_DISABLED are reported
 * from endrx_isr.
 */
static void rxto_isr(const struct device *dev)
{
	static const uint8_t dirty;
	struct uarte_nrfx_data *data = get_dev_data(dev);
	struct uart_event evt = {
		.type = UART_RX_BUF_RELEASED,
		.data.rx_buf.buf = data->async->rx_buf,
	};
	user_callback(dev, &evt);

	data->async->rx_buf = NULL;
	if (data->async->rx_next_buf) {
		evt.type = UART_RX_BUF_RELEASED;
		evt.data.rx_buf.buf = data->async->rx_next_buf;
		user_callback(dev, &evt);
		data->async->rx_next_buf = NULL;
	}

	/* Flushing RX fifo requires buffer bigger than 4 bytes to empty fifo */
	uarte_prev_rx_amount = nrf_uarte_rx_amount_get(get_uarte_instance(dev));
	uarte_prev_dirty = dirty;
	memset(po_flush_buf, dirty, sizeof(po_flush_buf));
	nrf_uarte_rx_buffer_set(get_uarte_instance(dev), po_flush_buf, 5);
	/* Final part of handling RXTO event is in ENDRX interrupt handler.
	 * ENDRX is generated as a result of FLUSHRX task.
	 */
	nrf_uarte_task_trigger(get_uarte_instance(dev), NRF_UARTE_TASK_FLUSHRX);
}

static void txstopped_isr(const struct device *dev)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	int key;

	if (!data->async->tx_buf) {
		/* If there is a pending tx request, it means that uart_tx()
		 * was called when there was ongoing uart_poll_out. Handling
		 * TXSTOPPED interrupt means that uart_poll_out has completed.
		 */
		if (data->async->pend_tx_buf) {
			key = irq_lock();

			if (nrf_uarte_event_check(uarte,
						NRF_UARTE_EVENT_TXSTOPPED)) {
				data->async->tx_buf = data->async->pend_tx_buf;
				data->async->pend_tx_buf = NULL;
				data->async->tx_amount = -1;
				tx_start(uarte, data->async->tx_buf,
					 data->async->tx_size);
			}

			irq_unlock(key);
		}
		return;
	}

	k_timer_stop(&data->async->tx_timeout_timer);

	key = irq_lock();
	size_t amount = (data->async->tx_amount >= 0) ?
			data->async->tx_amount : nrf_uarte_tx_amount_get(uarte);

	irq_unlock(key);

	struct uart_event evt = {
		.data.tx.buf = data->async->tx_buf,
		.data.tx.len = amount,
	};
	if (amount == data->async->tx_size) {
		evt.type = UART_TX_DONE;
	} else {
		evt.type = UART_TX_ABORTED;
	}

	nrf_uarte_int_disable(uarte, NRF_UARTE_INT_TXSTOPPED_MASK);
	data->async->tx_buf = NULL;
	data->async->tx_size = 0;

	user_callback(dev, &evt);
}

static void uarte_nrfx_isr_async(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	struct uarte_nrfx_data *data = get_dev_data(dev);

	if (!hw_rx_counting_enabled(data)
	    && nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXDRDY)) {
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXDRDY);
		data->async->rx_cnt.cnt++;
		return;
	}

	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ERROR)) {
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ERROR);
		error_isr(dev);
	}

	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
		endrx_isr(dev);
	}

	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXSTARTED)) {
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXSTARTED);
		rxstarted_isr(dev);
	}

	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXTO)) {
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXTO);
		rxto_isr(dev);
	}

	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)
	    && nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK)) {
		endtx_isr(dev);
	}

	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)
	    && nrf_uarte_int_enable_check(uarte,
					  NRF_UARTE_INT_TXSTOPPED_MASK)) {
		txstopped_isr(dev);
	}
}

#endif /* CONFIG_UART_ASYNC_API */

/**
 * @brief Poll the device for input.
 *
 * @param dev UARTE device struct
 * @param c Pointer to character
 *
 * @return 0 if a character arrived, -1 if the input buffer is empty.
 */
static int uarte_nrfx_poll_in(const struct device *dev, unsigned char *c)
{

	const struct uarte_nrfx_data *data = get_dev_data(dev);
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

#ifdef CONFIG_UART_ASYNC_API
	if (data->async) {
		return -ENOTSUP;
	}
#endif

	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
		return -1;
	}

	*c = data->rx_data;

	/* clear the interrupt */
	nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);

	return 0;
}

/**
 * @brief Output a character in polled mode.
 *
 * @param dev UARTE device struct
 * @param c Character to send
 */
static void uarte_nrfx_poll_out(const struct device *dev, unsigned char c)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	int key;

#ifdef CONFIG_PM_DEVICE
	if (data->pm_state != DEVICE_PM_ACTIVE_STATE) {
		return;
	}
#endif
	if (isr_mode) {
		while (1) {
			key = irq_lock();
			if (is_tx_ready(dev)) {
#if CONFIG_UART_ASYNC_API
				if (data->async && data->async->tx_size &&
					data->async->tx_amount < 0) {
					data->async->tx_amount =
						nrf_uarte_tx_amount_get(uarte);
				}
#endif
				break;
			}

			irq_unlock(key);
		}
	} else {
		key = wait_tx_ready(dev);
	}

	/* At this point we should have irq locked and any previous transfer
	 * completed. Transfer can be started, no need to wait for completion.
	 */
	data->char_out = c;
	tx_start(uarte, &data->char_out, 1);

	irq_unlock(key);
}


#ifdef UARTE_INTERRUPT_DRIVEN
/** Interrupt driven FIFO fill function */
static int uarte_nrfx_fifo_fill(const struct device *dev,
				const uint8_t *tx_data,
				int len)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	struct uarte_nrfx_data *data = get_dev_data(dev);

	len = MIN(len, data->int_driven->tx_buff_size);
	if (!atomic_cas(&data->int_driven->fifo_fill_lock, 0, 1)) {
		return 0;
	}

	/* Copy data to RAM buffer for EasyDMA transfer */
	for (int i = 0; i < len; i++) {
		data->int_driven->tx_buffer[i] = tx_data[i];
	}

	int key = irq_lock();

	if (!is_tx_ready(dev)) {
		data->int_driven->fifo_fill_lock = 0;
		len = 0;
	} else {
		tx_start(uarte, data->int_driven->tx_buffer, len);
	}

	irq_unlock(key);

	return len;
}

/** Interrupt driven FIFO read function */
static int uarte_nrfx_fifo_read(const struct device *dev,
				uint8_t *rx_data,
				const int size)
{
	int num_rx = 0;
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	const struct uarte_nrfx_data *data = get_dev_data(dev);

	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
		/* Clear the interrupt */
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);

		/* Receive a character */
		rx_data[num_rx++] = (uint8_t)data->rx_data;

		nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);
	}

	return num_rx;
}

/** Interrupt driven transfer enabling function */
static void uarte_nrfx_irq_tx_enable(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	struct uarte_nrfx_data *data = get_dev_data(dev);
	int key = irq_lock();

	data->int_driven->disable_tx_irq = false;
	nrf_uarte_int_enable(uarte, NRF_UARTE_INT_TXSTOPPED_MASK);

	irq_unlock(key);
}

/** Interrupt driven transfer disabling function */
static void uarte_nrfx_irq_tx_disable(const struct device *dev)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);
	/* TX IRQ will be disabled after current transmission is finished */
	data->int_driven->disable_tx_irq = true;
}

/** Interrupt driven transfer ready function */
static int uarte_nrfx_irq_tx_ready_complete(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	struct uarte_nrfx_data *data = get_dev_data(dev);

	/* ENDTX flag is always on so that ISR is called when we enable TX IRQ.
	 * Because of that we have to explicitly check if ENDTX interrupt is
	 * enabled, otherwise this function would always return true no matter
	 * what would be the source of interrupt.
	 */
	bool ready = !data->int_driven->disable_tx_irq &&
		     nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) &&
		     nrf_uarte_int_enable_check(uarte,
						NRF_UARTE_INT_TXSTOPPED_MASK);

	if (ready) {
		data->int_driven->fifo_fill_lock = 0;
	}

	return ready;
}

static int uarte_nrfx_irq_rx_ready(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX);
}

/** Interrupt driven receiver enabling function */
static void uarte_nrfx_irq_rx_enable(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	nrf_uarte_int_enable(uarte, NRF_UARTE_INT_ENDRX_MASK);
}

/** Interrupt driven receiver disabling function */
static void uarte_nrfx_irq_rx_disable(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	nrf_uarte_int_disable(uarte, NRF_UARTE_INT_ENDRX_MASK);
}

/** Interrupt driven error enabling function */
static void uarte_nrfx_irq_err_enable(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	nrf_uarte_int_enable(uarte, NRF_UARTE_INT_ERROR_MASK);
}

/** Interrupt driven error disabling function */
static void uarte_nrfx_irq_err_disable(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	nrf_uarte_int_disable(uarte, NRF_UARTE_INT_ERROR_MASK);
}

/** Interrupt driven pending status function */
static int uarte_nrfx_irq_is_pending(const struct device *dev)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	return ((nrf_uarte_int_enable_check(uarte,
					    NRF_UARTE_INT_TXSTOPPED_MASK) &&
		 uarte_nrfx_irq_tx_ready_complete(dev))
		||
		(nrf_uarte_int_enable_check(uarte,
					    NRF_UARTE_INT_ENDRX_MASK) &&
		 uarte_nrfx_irq_rx_ready(dev)));
}

/** Interrupt driven interrupt update function */
static int uarte_nrfx_irq_update(const struct device *dev)
{
	return 1;
}

/** Set the callback function */
static void uarte_nrfx_irq_callback_set(const struct device *dev,
					uart_irq_callback_user_data_t cb,
					void *cb_data)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);

	data->int_driven->cb = cb;
	data->int_driven->cb_data = cb_data;
}
#endif /* UARTE_INTERRUPT_DRIVEN */

static const struct uart_driver_api uart_nrfx_uarte_driver_api = {
	.poll_in		= uarte_nrfx_poll_in,
	.poll_out		= uarte_nrfx_poll_out,
	.err_check		= uarte_nrfx_err_check,
	.configure              = uarte_nrfx_configure,
	.config_get             = uarte_nrfx_config_get,
#ifdef CONFIG_UART_ASYNC_API
	.callback_set		= uarte_nrfx_callback_set,
	.tx			= uarte_nrfx_tx,
	.tx_abort		= uarte_nrfx_tx_abort,
	.rx_enable		= uarte_nrfx_rx_enable,
	.rx_buf_rsp		= uarte_nrfx_rx_buf_rsp,
	.rx_disable		= uarte_nrfx_rx_disable,
#endif /* CONFIG_UART_ASYNC_API */
#ifdef UARTE_INTERRUPT_DRIVEN
	.fifo_fill		= uarte_nrfx_fifo_fill,
	.fifo_read		= uarte_nrfx_fifo_read,
	.irq_tx_enable		= uarte_nrfx_irq_tx_enable,
	.irq_tx_disable		= uarte_nrfx_irq_tx_disable,
	.irq_tx_ready		= uarte_nrfx_irq_tx_ready_complete,
	.irq_rx_enable		= uarte_nrfx_irq_rx_enable,
	.irq_rx_disable		= uarte_nrfx_irq_rx_disable,
	.irq_tx_complete	= uarte_nrfx_irq_tx_ready_complete,
	.irq_rx_ready		= uarte_nrfx_irq_rx_ready,
	.irq_err_enable		= uarte_nrfx_irq_err_enable,
	.irq_err_disable	= uarte_nrfx_irq_err_disable,
	.irq_is_pending		= uarte_nrfx_irq_is_pending,
	.irq_update		= uarte_nrfx_irq_update,
	.irq_callback_set	= uarte_nrfx_irq_callback_set,
#endif /* UARTE_INTERRUPT_DRIVEN */
};

static int endtx_stoptx_ppi_init(NRF_UARTE_Type *uarte,
				 struct uarte_nrfx_data *data)
{
	nrfx_err_t ret;

	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
	if (ret != NRFX_SUCCESS) {
		LOG_ERR("Failed to allocate PPI Channel");
		return -EIO;
	}

	nrfx_gppi_channel_endpoints_setup(data->ppi_ch_endtx,
		nrf_uarte_event_address_get(uarte, NRF_UARTE_EVENT_ENDTX),
		nrf_uarte_task_address_get(uarte, NRF_UARTE_TASK_STOPTX));
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));

	return 0;
}

static int uarte_instance_init(const struct device *dev,
			       const struct uarte_init_config *config,
			       uint8_t interrupts_active)
{
	int err;
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	struct uarte_nrfx_data *data = get_dev_data(dev);

	nrf_uarte_disable(uarte);

	data->dev = dev;

	nrf_gpio_pin_write(config->pseltxd, 1);
	nrf_gpio_cfg_output(config->pseltxd);

	if (config->pselrxd !=  NRF_UARTE_PSEL_DISCONNECTED) {
		nrf_gpio_cfg_input(config->pselrxd, NRF_GPIO_PIN_NOPULL);
	}

	nrf_uarte_txrx_pins_set(uarte, config->pseltxd, config->pselrxd);

	if (config->pselcts != NRF_UARTE_PSEL_DISCONNECTED) {
		nrf_gpio_cfg_input(config->pselcts, NRF_GPIO_PIN_NOPULL);
	}

	if (config->pselrts != NRF_UARTE_PSEL_DISCONNECTED) {
		nrf_gpio_pin_write(config->pselrts, 1);
		nrf_gpio_cfg_output(config->pselrts);
	}

	nrf_uarte_hwfc_pins_set(uarte, config->pselrts, config->pselcts);

	err = uarte_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
	if (err) {
		return err;
	}

#ifdef CONFIG_PM_DEVICE
	data->pm_state = DEVICE_PM_ACTIVE_STATE;
#endif

	if (get_dev_config(dev)->ppi_endtx) {
		err = endtx_stoptx_ppi_init(uarte, data);
		if (err < 0) {
			return err;
		}
	}


#ifdef CONFIG_UART_ASYNC_API
	if (data->async) {
		err = uarte_nrfx_init(dev);
		if (err < 0) {
			return err;
		}
	} else
#endif
	{
		/* Enable receiver and transmitter */
		nrf_uarte_enable(uarte);

		if (config->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
			nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);

			nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
			nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);
		}
	}

	if (!get_dev_config(dev)->ppi_endtx) {
		nrf_uarte_int_enable(uarte, NRF_UARTE_INT_ENDTX_MASK);
	}

	/* Set TXSTOPPED event by requesting fake (zero-length) transfer.
	 * Pointer to RAM variable (data->tx_buffer) is set because otherwise
	 * such operation may result in HardFault or RAM corruption.
	 */
	nrf_uarte_tx_buffer_set(uarte, &data->char_out, 0);
	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTTX);

	/* switch off transmitter to save an energy */
	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPTX);

	return 0;
}

#ifdef CONFIG_PM_DEVICE

static void uarte_nrfx_pins_enable(const struct device *dev, bool enable)
{
	if (!get_dev_config(dev)->gpio_mgmt) {
		return;
	}

	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	uint32_t tx_pin = nrf_uarte_tx_pin_get(uarte);
	uint32_t rx_pin = nrf_uarte_rx_pin_get(uarte);
	uint32_t cts_pin = nrf_uarte_cts_pin_get(uarte);
	uint32_t rts_pin = nrf_uarte_rts_pin_get(uarte);

	if (enable) {
		nrf_gpio_pin_write(tx_pin, 1);
		nrf_gpio_cfg_output(tx_pin);
		if (rx_pin != NRF_UARTE_PSEL_DISCONNECTED) {
			nrf_gpio_cfg_input(rx_pin, NRF_GPIO_PIN_NOPULL);
		}

		if (IS_RTS_PIN_SET(get_dev_config(dev)->rts_cts_pins_set)) {
			nrf_gpio_pin_write(rts_pin, 1);
			nrf_gpio_cfg_output(rts_pin);
		}

		if (IS_CTS_PIN_SET(get_dev_config(dev)->rts_cts_pins_set)) {
			nrf_gpio_cfg_input(cts_pin,
					   NRF_GPIO_PIN_NOPULL);
		}
	} else {
		nrf_gpio_cfg_default(tx_pin);
		if (rx_pin != NRF_UARTE_PSEL_DISCONNECTED) {
			nrf_gpio_cfg_default(rx_pin);
		}

		if (IS_RTS_PIN_SET(get_dev_config(dev)->rts_cts_pins_set)) {
			nrf_gpio_cfg_default(rts_pin);
		}

		if (IS_CTS_PIN_SET(get_dev_config(dev)->rts_cts_pins_set)) {
			nrf_gpio_cfg_default(cts_pin);
		}
	}
}

static void uarte_nrfx_set_power_state(const struct device *dev,
				       uint32_t new_state)
{
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	struct uarte_nrfx_data *data = get_dev_data(dev);

	if (new_state == DEVICE_PM_ACTIVE_STATE) {
		uarte_nrfx_pins_enable(dev, true);
		nrf_uarte_enable(uarte);

		data->pm_state = new_state;

#ifdef CONFIG_UART_ASYNC_API
		if (hw_rx_counting_enabled(get_dev_data(dev))) {
			nrfx_timer_enable(&get_dev_config(dev)->timer);
		}
		if (get_dev_data(dev)->async) {
			return;
		}
#endif
		if (nrf_uarte_rx_pin_get(uarte) !=
			NRF_UARTE_PSEL_DISCONNECTED) {

			nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
			nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);
#ifdef UARTE_INTERRUPT_DRIVEN
			if (data->int_driven &&
			    data->int_driven->rx_irq_enabled) {
				nrf_uarte_int_enable(uarte,
						     NRF_UARTE_INT_ENDRX_MASK);
			}
#endif
		}
	} else {
		__ASSERT_NO_MSG(new_state == DEVICE_PM_LOW_POWER_STATE ||
				new_state == DEVICE_PM_SUSPEND_STATE ||
				new_state == DEVICE_PM_OFF_STATE);

		/* if pm is already not active, driver will stay indefinitely
		 * in while loop waiting for event NRF_UARTE_EVENT_RXTO
		 */
		if (data->pm_state != DEVICE_PM_ACTIVE_STATE) {
			return;
		}

		data->pm_state = new_state;

		/* Disabling UART requires stopping RX, but stop RX event is
		 * only sent after each RX if async UART API is used.
		 */
#ifdef CONFIG_UART_ASYNC_API
		if (hw_rx_counting_enabled(get_dev_data(dev))) {
			nrfx_timer_disable(&get_dev_config(dev)->timer);
			/* Timer/counter value is reset when disabled. */
			data->async->rx_total_byte_cnt = 0;
			data->async->rx_total_user_byte_cnt = 0;
		}
		if (get_dev_data(dev)->async) {
			/* Wait for the transmitter to go idle.
			 * While the async API can wait for transmission to
			 * complete before disabling the peripheral, the poll
			 * API exits before the character is sent on the wire.
			 * If the transmission is ongoing when the peripheral
			 * is disabled, the ENDTX and TXSTOPPED events will
			 * never be generated. This will block the driver in
			 * any future calls to poll_out.
			 */
			irq_unlock(wait_tx_ready(dev));
			nrf_uarte_disable(uarte);
			uarte_nrfx_pins_enable(dev, false);
			return;
		}
#endif
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXSTARTED)) {
#ifdef UARTE_INTERRUPT_DRIVEN
			if (data->int_driven) {
				data->int_driven->rx_irq_enabled =
					nrf_uarte_int_enable_check(uarte,
						NRF_UARTE_INT_ENDRX_MASK);
				if (data->int_driven->rx_irq_enabled) {
					nrf_uarte_int_disable(uarte,
						NRF_UARTE_INT_ENDRX_MASK);
				}
			}
#endif
			nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPRX);
			while (!nrf_uarte_event_check(uarte,
						      NRF_UARTE_EVENT_RXTO)) {
				/* Busy wait for event to register */
			}
			nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXSTARTED);
			nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXTO);
		}
		nrf_uarte_disable(uarte);
		uarte_nrfx_pins_enable(dev, false);
	}
}

static int uarte_nrfx_pm_control(const struct device *dev,
				 uint32_t ctrl_command,
				 void *context, device_pm_cb cb, void *arg)
{
	struct uarte_nrfx_data *data = get_dev_data(dev);

	if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
		uint32_t new_state = *((const uint32_t *)context);

		if (new_state != data->pm_state) {
			uarte_nrfx_set_power_state(dev, new_state);
		}
	} else {
		__ASSERT_NO_MSG(ctrl_command == DEVICE_PM_GET_POWER_STATE);
		*((uint32_t *)context) = data->pm_state;
	}

	if (cb) {
		cb(dev, 0, context, arg);
	}

	return 0;
}
#endif /* CONFIG_PM_DEVICE */

#define UARTE(idx)			DT_NODELABEL(uart##idx)
#define UARTE_HAS_PROP(idx, prop)	DT_NODE_HAS_PROP(UARTE(idx), prop)
#define UARTE_PROP(idx, prop)		DT_PROP(UARTE(idx), prop)

#define UARTE_PSEL(idx, pin_prop)					       \
	COND_CODE_1(UARTE_HAS_PROP(idx, pin_prop),			       \
		    (UARTE_PROP(idx, pin_prop)),			       \
		    (NRF_UARTE_PSEL_DISCONNECTED))

#define HWFC_AVAILABLE(idx)					       \
	(UARTE_HAS_PROP(idx, rts_pin) || UARTE_HAS_PROP(idx, cts_pin))

#define UARTE_IRQ_CONFIGURE(idx, isr_handler)				       \
	do {								       \
		IRQ_CONNECT(DT_IRQN(UARTE(idx)), DT_IRQ(UARTE(idx), priority), \
			    isr_handler, DEVICE_DT_GET(UARTE(idx)), 0); \
		irq_enable(DT_IRQN(UARTE(idx)));			       \
	} while (0)

#define HWFC_CONFIG_CHECK(idx) \
	BUILD_ASSERT( \
		(UARTE_PROP(idx, hw_flow_control) && HWFC_AVAILABLE(idx)) \
		|| \
		!UARTE_PROP(idx, hw_flow_control) \
	)

#define UART_NRF_UARTE_DEVICE(idx)					       \
	HWFC_CONFIG_CHECK(idx);						       \
	UARTE_INT_DRIVEN(idx);						       \
	UARTE_ASYNC(idx);						       \
	static struct uarte_nrfx_data uarte_##idx##_data = {		       \
		UARTE_CONFIG(idx),					       \
		IF_ENABLED(CONFIG_UART_##idx##_ASYNC,			       \
			    (.async = &uarte##idx##_async,))		       \
		IF_ENABLED(CONFIG_UART_##idx##_INTERRUPT_DRIVEN,	       \
			    (.int_driven = &uarte##idx##_int_driven,))	       \
	};								       \
	static const struct uarte_nrfx_config uarte_##idx##z_config = {	       \
		.uarte_regs = (NRF_UARTE_Type *)DT_REG_ADDR(UARTE(idx)),       \
		.rts_cts_pins_set =					       \
			(UARTE_HAS_PROP(idx, rts_pin) ? RTS_PIN_SET_MASK : 0) |\
			(UARTE_HAS_PROP(idx, cts_pin) ? CTS_PIN_SET_MASK : 0), \
		.gpio_mgmt = IS_ENABLED(CONFIG_UART_##idx##_GPIO_MANAGEMENT),  \
		.ppi_endtx = IS_ENABLED(CONFIG_UART_##idx##_ENHANCED_POLL_OUT),\
		IF_ENABLED(CONFIG_UART_##idx##_NRF_HW_ASYNC,		       \
			(.timer = NRFX_TIMER_INSTANCE(			       \
				CONFIG_UART_##idx##_NRF_HW_ASYNC_TIMER),))     \
	};								       \
	static int uarte_##idx##_init(const struct device *dev)		       \
	{								       \
		const struct uarte_init_config init_config = {		       \
			.pseltxd = UARTE_PROP(idx, tx_pin),  /* must be set */ \
			.pselrxd = UARTE_PSEL(idx, rx_pin),  /* optional */    \
			.pselcts = UARTE_PSEL(idx, cts_pin), /* optional */    \
			.pselrts = UARTE_PSEL(idx, rts_pin), /* optional */    \
		};							       \
		COND_CODE_1(CONFIG_UART_##idx##_ASYNC,			       \
			   (UARTE_IRQ_CONFIGURE(idx, uarte_nrfx_isr_async);),  \
			   (UARTE_IRQ_CONFIGURE(idx, uarte_nrfx_isr_int);))    \
		return uarte_instance_init(				       \
			dev,						       \
			&init_config,					       \
			IS_ENABLED(CONFIG_UART_##idx##_INTERRUPT_DRIVEN));     \
	}								       \
	DEVICE_DT_DEFINE(UARTE(idx),					       \
		      uarte_##idx##_init,				       \
		      uarte_nrfx_pm_control,				       \
		      &uarte_##idx##_data,				       \
		      &uarte_##idx##z_config,				       \
		      PRE_KERNEL_1,					       \
		      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,		       \
		      &uart_nrfx_uarte_driver_api)

#define UARTE_CONFIG(idx)						       \
	.uart_config = {						       \
		.baudrate = UARTE_PROP(idx, current_speed),		       \
		.data_bits = UART_CFG_DATA_BITS_8,			       \
		.stop_bits = UART_CFG_STOP_BITS_1,			       \
		.parity = IS_ENABLED(CONFIG_UART_##idx##_NRF_PARITY_BIT)       \
			  ? UART_CFG_PARITY_EVEN			       \
			  : UART_CFG_PARITY_NONE,			       \
		.flow_ctrl = UARTE_PROP(idx, hw_flow_control)  \
			     ? UART_CFG_FLOW_CTRL_RTS_CTS		       \
			     : UART_CFG_FLOW_CTRL_NONE,			       \
	}

#define UARTE_ASYNC(idx)						       \
	IF_ENABLED(CONFIG_UART_##idx##_ASYNC,				       \
		(struct uarte_async_cb uarte##idx##_async = {		       \
			.hw_rx_counting =				       \
				IS_ENABLED(CONFIG_UART_##idx##_NRF_HW_ASYNC),  \
		}))

#define UARTE_INT_DRIVEN(idx)						       \
	IF_ENABLED(CONFIG_UART_##idx##_INTERRUPT_DRIVEN,	       \
		(static uint8_t uarte##idx##_tx_buffer[\
			MIN(CONFIG_UART_##idx##_NRF_TX_BUFFER_SIZE,	       \
			    BIT_MASK(UARTE##idx##_EASYDMA_MAXCNT_SIZE))];      \
		 static struct uarte_nrfx_int_driven			       \
			uarte##idx##_int_driven = {			       \
				.tx_buffer = uarte##idx##_tx_buffer,	       \
				.tx_buff_size = sizeof(uarte##idx##_tx_buffer),\
			};))

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
#endif

#ifdef CONFIG_UART_1_NRF_UARTE
UART_NRF_UARTE_DEVICE(1);
#endif

#ifdef CONFIG_UART_2_NRF_UARTE
UART_NRF_UARTE_DEVICE(2);
#endif

#ifdef CONFIG_UART_3_NRF_UARTE
UART_NRF_UARTE_DEVICE(3);
#endif

prj.conf

# NEWLIB C
CONFIG_NEWLIB_LIBC=y
CONFIG_NEWLIB_LIBC_FLOAT_PRINTF=y

CONFIG_SERIAL=y
CONFIG_UART_ASYNC_API=y
CONFIG_NRFX_UARTE0=y


# General
# CONFIG_REBOOT=y
# CONFIG_EVENT_MANAGER=y
# CONFIG_LINKER_ORPHAN_SECTION_PLACE=y
# CONFIG_SPEED_OPTIMIZATIONS=y
# CONFIG_DEVICE_POWER_MANAGEMENT=y
# CONFIG_PM_POLICY_APP=y

#  # UART
# CONFIG_SERIAL=y
# CONFIG_UART_INTERRUPT_DRIVEN=y
# CONFIG_UART_0_INTERRUPT_DRIVEN=n
# CONFIG_UART_1_INTERRUPT_DRIVEN=n
# CONFIG_UART_LINE_CTRL=y
# CONFIG_UART_ASYNC_API=y
# CONFIG_UART_0_ASYNC=y
# CONFIG_UART_1_ASYNC=y
# CONFIG_UART_0_NRF_HW_ASYNC=y
# CONFIG_UART_1_NRF_HW_ASYNC=y
# CONFIG_UART_0_NRF_HW_ASYNC_TIMER=1
# CONFIG_UART_1_NRF_HW_ASYNC_TIMER=2
# CONFIG_NRFX_UARTE=y
# CONFIG_NRFX_UARTE0=y
# CONFIG_NRFX_UARTE1=y
# CONFIG_NRFX_TIMER=y
# CONFIG_NRFX_TIMER1=y
# CONFIG_NRFX_TIMER2=y
# CONFIG_NRFX_PPI=y



CONFIG_NRF_MODEM_LIB=y
CONFIG_NRF_MODEM_LIB_SYS_INIT=n

# Modem information
CONFIG_MODEM_INFO=y

CONFIG_NETWORKING=y
CONFIG_NET_TCP=y
CONFIG_NET_SOCKETS=y
CONFIG_NET_SOCKETS_POSIX_NAMES=y
CONFIG_NET_NATIVE=n
CONFIG_NET_IPV6=n
CONFIG_NET_IPV4=y
CONFIG_NET_SOCKETS_POLL_MAX=4
CONFIG_NET_CONNECTION_MANAGER=y

# Network buffers
CONFIG_NET_PKT_RX_COUNT=16
CONFIG_NET_PKT_TX_COUNT=16
CONFIG_NET_BUF_RX_COUNT=80
CONFIG_NET_BUF_TX_COUNT=80
CONFIG_NET_CONTEXT_NET_PKT_POOL=y

#CONFIG_NET_IF_MAX_IPV4_COUNT=2
#CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT=3

#CONFIG_DNS_SERVER_IP_ADDRESSES=y
#CONFIG_DNS_SERVER1="8.8.8.8"

#CONFIG_DNS_RESOLVER=y
#CONFIG_DNS_RESOLVER_ADDITIONAL_BUF_CTR=2
#CONFIG_SNTP=y

CONFIG_HTTP_CLIENT=y
CONFIG_HTTP_PARSER_URL=y

CONFIG_HEAP_MEM_POOL_SIZE=65536
CONFIG_MAIN_STACK_SIZE=8192
CONFIG_PRIVILEGED_STACK_SIZE=8192
CONFIG_ISR_STACK_SIZE=8192
#CONFIG_AT_CMD_THREAD_STACK_SIZE=4096

CONFIG_MODEM_KEY_MGMT=y
CONFIG_LTE_LINK_CONTROL=y
CONFIG_LTE_AUTO_INIT_AND_CONNECT=n


# CONFIG_DFU_TARGET=y

CONFIG_BOOTLOADER_MCUBOOT=y
#CONFIG_BOOT_ENCRYPT_RSA=n
#CONFIG_BOOT_SIGNATURE_TYPE_RSA=y
#CONFIG_BOOT_SIGNATURE_TYPE_ECDSA_P256=n
#CONFIG_BOOT_SIGNATURE_KEY_FILE="tinykey.pem"

CONFIG_MCUBOOT_IMAGE_VERSION="1.0.10"

CONFIG_HWINFO=y

CONFIG_FLASH=y
CONFIG_FLASH_PAGE_LAYOUT=y
CONFIG_FLASH_MAP=y


CONFIG_IMG_MANAGER=y
CONFIG_FLASH=y
CONFIG_IMG_ERASE_PROGRESSIVELY=y

CONFIG_LOG=y
CONFIG_LOG_PRINTK=y
CONFIG_LOG_BACKEND_UART=n
CONFIG_LOG_IMMEDIATE=n

CONFIG_OBJECT_TRACING=y
CONFIG_THREAD_MONITOR=y

CONFIG_ASSERT=y

CONFIG_BASE64=y

#CONFIG_FILE_SYSTEM=y
#CONFIG_FILE_SYSTEM_LITTLEFS=y

#CONFIG_ASSERT=n
#CONFIG_LOG_BUFFER_SIZE=1024
#CONFIG_LOG_STRDUP_BUF_COUNT=2
#CONFIG_LOG_STRDUP_MAX_STRING=512
#CONFIG_LOG_MIPI_SYST_ENABLE=y
#CONFIG_LOG_BACKEND_UART_SYST_ENABLE=y
#CONFIG_SOC_LOG_LEVEL_OFF=y
#CONFIG_ARCH_LOG_LEVEL_OFF=y
#CONFIG_KERNEL_LOG_LEVEL_OFF=y
#CONFIG_LOG_RUNTIME_FILTERING=n
#CONFIG_MAIN_THREAD_PRIORITY=10
#CONFIG_LOG_FUNC_NAME_PREFIX_DBG=n
#CONFIG_LOG_PROCESS_THREAD=y
#CONFIG_LOG_PROCESS_THREAD_SLEEP_MS=100
#CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD=2
#CONFIG_LOG_PRINTK_MAX_STRING_LENGTH=256
CONFIG_LOG_PROCESS_THREAD_STACK_SIZE=8192


CONFIG_SECURE_BOOT=y
#CONFIG_BUILD_S1_VARIANT=y
CONFIG_SB_SIGNING_KEY_FILE="configuration/tinycarrierv1/tiny_b0_priv.pem"

CONFIG_DFU_TARGET=y
CONFIG_DFU_TARGET_MCUBOOT=y
CONFIG_DFU_TARGET_MODEM_DELTA=y
CONFIG_DFU_TARGET_FULL_MODEM=n

CONFIG_MCUMGR=y
CONFIG_MCUMGR_CMD_IMG_MGMT=y

CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096

CONFIG_BUILD_S1_VARIANT=y
CONFIG_FW_INFO=y
CONFIG_FW_INFO_FIRMWARE_VERSION=1

prj.overlay

&uart0 {
	compatible = "nordic,nrf-uarte";
};

[Susheel Nuguru]

I haven't seen this before and cannot find any reference to a thread that had similar issue. 

Can you please add this in your proj.conf and show us your detail log on the hardfault

CONFIG_THREAD_ANALYZER=y
CONFIG_THREAD_NAME=y
CONFIG_THREAD_MONITOR=y
CONFIG_DEBUG_OPTIMIZATIONS=y
CONFIG_STACK_SENTINEL=y

I am trying to see the name of the thread that caused this fault be enabling some debug options.

[ismail_embedded]

Firstly, there are some warning which some of them e.g. Warning (111) and (114) made me anxious a bit.

ompilation unit with DWARF5 debug information detected - DWARF5 is not yet fully supported
Warning (104): The ELF parser encountered an invalid location list reference.
Warning (111): ELF data section '.debug_line' has an unexpected byte size.
Warning (114): The address mapping table decoder encountered an invalid directory index.
File.Open ("/home/ismail/xxx/yyy/build/zephyr/zephyr.elf");
File.Open: completed in 329 ms
Program segments:
  Address         Size         Code      RO Data      RW Data      ZI Data    Flg
---------    ---------    ---------    ---------    ---------    ---------    ---
 0005A3D4            0            0            0            0            0    R
 00034200      182 328      156 112       25 696          520            0    RWE
 200144E8           24            0            0           24            0    RW
 20014500        1 889            0          132        1 757            0    RW
 20014C68      156 901            0            0      156 901            0    RW
---------    ---------    ---------    ---------    ---------    ---------    ---
   Total:      341 142      156 112       25 828      159 202            0

I am not clear, where this detail log would be outputted from in OZONE ? I added these configs and nothing changed.

When I hitted the play , it is prompting immadiately Cortex-M Hardfault Exception and shows the result as in the below.

[ismail_embedded]

Any assumption ?

This is the build script.

west build -b custom_boardns app/hub -- -DCONFIG_SECURE_BOOT=y -DCONFIG_BOOTLOADER_MCUBOOT=y

[Susheel Nuguru]

Ismail, sorry for late response. I wont be able to test this today, But will  ask an expert today and will be able to test it tomorrow.  If you have logs enabled I expected that the hardfault details are thrown out through the logs.

Which backend are you using for the logs? I see in your config that you have disabled uart as the backend for logs.

[ismail_embedded]

I am using vscode for build system and ozone for the debugging. CONFIG_LOG=y right now but software crashes in so early stage of boot. I am suspecting of secure_boot option or ns build. I created http_client application from samples for nrf9160 with _ns build. Similar error happens, sometimes stackerr, sometimes preciserr happens. The legacy code is working with app_update.bin build if I use bootloader to test changes I made but this is not an optimal way.

As far as I debugged, the last point programm halted is here in boot process.

This function is calling from function z_cstart->z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1)

/**
 * @brief Execute all the init entry initialization functions at a given level
 *
 * @details Invokes the initialization routine for each init entry object
 * created by the INIT_ENTRY_DEFINE() macro using the specified level.
 * The linker script places the init entry objects in memory in the order
 * they need to be invoked, with symbols indicating where one level leaves
 * off and the next one begins.
 *
 * @param level init level to run.
 */
void z_sys_init_run_level(int32_t level)
{
  static const struct init_entry *levels[] = {
    __init_PRE_KERNEL_1_start,
    __init_PRE_KERNEL_2_start,
    __init_POST_KERNEL_start,
    __init_APPLICATION_start,
#ifdef CONFIG_SMP
    __init_SMP_start,
#endif
    /* End marker */
    __init_end,
  };
  const struct init_entry *entry;


/*HERE BELOW WHERE ERROR PROMPTED*/
  for (entry = levels[level]; entry < levels[level+1]; entry++) {
    const struct device *dev = entry->dev;

    if (dev != NULL) {
      z_object_init(dev); 
    }
...

[Susheel Nuguru]

I am sorry for late response, was away sick with flu. Not sure if you have solved this by yourself.
I tried to replicate your setup and was unable to get your sources to compilable state. So I could not reproduce it at my desk.

But looking at the BFAR register address which 0x 04000 9500, this is the address of te UART1->ENABLE register. It seems like this register was being access in NS mode. I saw similar issue when one was trying to access the register in a wrong mode. I am not 100% sure if you also need to do this for UART1 but I thought that this is done automatically by the libs and drivers when you chose the one mode in the config file.

[ismail_embedded]

Yes. You catched a good point. As default, trustued firmware is using UART1 for logging issues. I thought that legacy coder might have missed this point. I saw there are some configuration which allow us to use UART1 in ns mode by disabling this logging purpose. I tried this option and disabling UART1 totaly also. Both of them did not worked. Interesting thing is same problem appeared again when I disabled UART1 but this time BFAR showed a different address which belongs to different peripheral. How can share my screen with you to review codebase ? I am suspecting of configurations.

[Susheel Nuguru]

ismail_embedded said:

I am suspecting of configurations.

can you share your .config file from your build folder? I can make this case private if you do not want others to see the details of config file.

[ismail_embedded]

Hi,

I was sick too :( Some Winter Facts :D

Here is .config file

 

CONFIG_MCUMGR_SMP_KFRAME_MTU=256
CONFIG_KFRAME_MCUMGR_RX_BUF_SIZE=512
CONFIG_KFRAME_MCUMGR_RX_BUF_COUNT=2
# CONFIG_SPI is not set
# CONFIG_I2C is not set
# CONFIG_KSCAN is not set
# CONFIG_WIFI is not set
# CONFIG_NET_L2_ETHERNET is not set
# CONFIG_MODEM is not set
# CONFIG_UART_INTERRUPT_DRIVEN is not set
# CONFIG_NET_IPV6 is not set
# CONFIG_NET_CONFIG_NEED_IPV6 is not set
CONFIG_BOARD="tinycarrier_nrf9160"
CONFIG_FLASH_LOAD_SIZE=0x30000
CONFIG_FLASH_LOAD_OFFSET=0x50000
CONFIG_SOC="nRF9160_SICA"
CONFIG_SOC_SERIES="nrf91"
CONFIG_NUM_IRQS=65
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768
# CONFIG_WATCHDOG is not set
CONFIG_HEAP_MEM_POOL_SIZE=65536
# CONFIG_UART_NS16550 is not set
CONFIG_GPIO=y
CONFIG_PM=y
# CONFIG_PM_DEEP_SLEEP_STATES is not set
CONFIG_HAS_POWER_STATE_DEEP_SLEEP_1=y
# CONFIG_PM_DEVICE is not set
CONFIG_SOC_HAS_TIMING_FUNCTIONS=y
CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT=y
# CONFIG_CORTEX_M_SYSTICK is not set
CONFIG_CLOCK_CONTROL=y
CONFIG_NRF_RTC_TIMER=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_FPU=y
CONFIG_ROM_START_OFFSET=0
CONFIG_FLASH_SIZE=1024
CONFIG_FLASH_BASE_ADDRESS=0x0
# CONFIG_GPIO_MCUX is not set
# CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS is not set
# CONFIG_TINYCRYPT is not set
# CONFIG_NET_L2_IEEE802154 is not set
CONFIG_SERIAL=y
# CONFIG_UART_PL011 is not set

#
# Modules
#

#
# Available modules.
#

#
# nrf (/home/ismail/hub/nrf)
#

#
# Nordic nRF Connect
#
CONFIG_MAIN_STACK_SIZE=8192
CONFIG_PRIVILEGED_STACK_SIZE=8192
# CONFIG_NCS_SAMPLES_DEFAULTS is not set
CONFIG_LOG_DEFAULT_LEVEL=3

#
# Bootloader
#
CONFIG_BUILD_S1_VARIANT=y
CONFIG_S1_VARIANT_IMAGE_NAME="mcuboot"
CONFIG_SECURE_BOOT=y
# CONFIG_B0_BUILD_STRATEGY_USE_HEX_FILE is not set
# CONFIG_B0_BUILD_STRATEGY_SKIP_BUILD is not set
CONFIG_B0_BUILD_STRATEGY_FROM_SOURCE=y
CONFIG_SB_PRIVATE_KEY_PROVIDED=y
CONFIG_SB_SIGNING_PYTHON=y
# CONFIG_SB_SIGNING_OPENSSL is not set
# CONFIG_SB_SIGNING_CUSTOM is not set
CONFIG_SB_SIGNING_KEY_FILE="configuration/tinycarrierv1/tiny_b0_priv.pem"
CONFIG_SB_SIGNING_COMMAND=""
CONFIG_SB_SIGNING_PUBLIC_KEY=""
CONFIG_SB_PUBLIC_KEY_FILES=""
# CONFIG_SB_DEBUG_SIGNATURE_PUBLIC_KEY_LAST is not set
CONFIG_SB_MONOTONIC_COUNTER=y
CONFIG_SB_NUM_VER_COUNTER_SLOTS=240
CONFIG_PM_PARTITION_SIZE_PROVISION=0x280
# CONFIG_B0_MIN_PARTITION_SIZE is not set
CONFIG_PM_PARTITION_SIZE_B0_IMAGE=0x8000
# CONFIG_SECURE_BOOT_CRYPTO is not set

#
# Secure Boot firmware validation
#
CONFIG_SB_VALIDATION_INFO_MAGIC=0x86518483
CONFIG_SB_VALIDATION_POINTER_MAGIC=0x6919b47e
CONFIG_SB_VALIDATION_INFO_CRYPTO_ID=1
CONFIG_SB_VALIDATION_INFO_VERSION=2
CONFIG_SB_VALIDATION_METADATA_OFFSET=0
CONFIG_SB_VALIDATE_FW_SIGNATURE=y
# end of Secure Boot firmware validation
# end of Bootloader

#
# Bluetooth Low Energy
#
CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096
# end of Bluetooth Low Energy

#
# DFU
#

#
# DFU
#
CONFIG_DFU_TARGET=y
CONFIG_DFU_TARGET_MCUBOOT=y
CONFIG_DFU_TARGET_STREAM=y
# CONFIG_DFU_TARGET_MCUBOOT_SAVE_PROGRESS is not set
CONFIG_DFU_TARGET_MODEM_DELTA=y
CONFIG_DFU_TARGET_MODEM_TIMEOUT=60
# CONFIG_DFU_TARGET_LOG_LEVEL_OFF is not set
# CONFIG_DFU_TARGET_LOG_LEVEL_ERR is not set
# CONFIG_DFU_TARGET_LOG_LEVEL_WRN is not set
CONFIG_DFU_TARGET_LOG_LEVEL_INF=y
# CONFIG_DFU_TARGET_LOG_LEVEL_DBG is not set
CONFIG_DFU_TARGET_LOG_LEVEL=3
# end of DFU
# end of DFU

# CONFIG_ESB is not set

#
# Peripheral CPU DFU (PCD)
#
# CONFIG_PCD is not set
# end of Peripheral CPU DFU (PCD)

#
# Networking
#

#
# Application protocols
#
# CONFIG_NRF_CLOUD is not set
# CONFIG_DOWNLOAD_CLIENT is not set
# CONFIG_AWS_IOT is not set
# CONFIG_AWS_JOBS is not set
# CONFIG_AZURE_IOT_HUB is not set
# CONFIG_CLOUD_API is not set

#
# Self-Registration (Zi ZHu Ce)
#
# CONFIG_ZZHC is not set
# end of Self-Registration (Zi ZHu Ce)

# CONFIG_ICAL_PARSER is not set
# CONFIG_FTP_CLIENT is not set
# CONFIG_COAP_UTILS is not set
# end of Application protocols
# end of Networking

#
# NFC
#
# CONFIG_NFC_NDEF is not set
# CONFIG_NFC_NDEF_PARSER is not set
# CONFIG_NFC_NDEF_PAYLOAD_TYPE_COMMON is not set
# CONFIG_NFC_T2T_PARSER is not set
# CONFIG_NFC_T4T_NDEF_FILE is not set
# CONFIG_NFC_T4T_ISODEP is not set
# CONFIG_NFC_T4T_APDU is not set
# CONFIG_NFC_T4T_CC_FILE is not set
# CONFIG_NFC_T4T_HL_PROCEDURE is not set
# CONFIG_NFC_PLATFORM is not set
# CONFIG_NFC_TNEP_TAG is not set
# CONFIG_NFC_TNEP_POLLER is not set
# CONFIG_NFC_TNEP_CH is not set
# end of NFC

# CONFIG_PROFILER is not set

#
# SPM
#
CONFIG_SPM=y
# CONFIG_SPM_BUILD_STRATEGY_USE_HEX_FILE is not set
# CONFIG_SPM_BUILD_STRATEGY_SKIP_BUILD is not set
CONFIG_SPM_BUILD_STRATEGY_FROM_SOURCE=y
# CONFIG_IS_SPM is not set
CONFIG_SPM_SECURE_SERVICES=y
CONFIG_SPM_SERVICE_RNG=y
CONFIG_SPM_SERVICE_READ=y
# CONFIG_SPM_SERVICE_REBOOT is not set
CONFIG_SPM_SERVICE_FIND_FIRMWARE_INFO=y
# CONFIG_SPM_SERVICE_S0_ACTIVE is not set
# CONFIG_SPM_SERVICE_PREVALIDATE is not set
# CONFIG_SPM_SERVICE_BUSY_WAIT is not set
CONFIG_ARM_ENTRY_VENEERS_LIB_NAME="spm/libspmsecureentries.a"
# end of SPM

CONFIG_FW_INFO=y
CONFIG_FW_INFO_OFFSET=0x200
CONFIG_FW_INFO_FIRMWARE_VERSION=1
CONFIG_FW_INFO_MAGIC_COMMON=0x281ee6de
CONFIG_FW_INFO_MAGIC_FIRMWARE_INFO=0x8fcebb4c
CONFIG_FW_INFO_MAGIC_EXT_API=0xb845acea
CONFIG_FW_INFO_HARDWARE_ID=91
CONFIG_FW_INFO_VERSION=2
CONFIG_FW_INFO_CRYPTO_ID=0
CONFIG_FW_INFO_MAGIC_COMPATIBILITY_ID=0
CONFIG_FW_INFO_MAGIC_LEN=12
CONFIG_FW_INFO_VALID_VAL=0x9102FFFF
CONFIG_EXT_API_PROVIDE_EXT_API_UNUSED=y
# CONFIG_EXT_API_PROVIDE_EXT_API_OPTIONAL is not set
# CONFIG_EXT_API_PROVIDE_EXT_API_REQUIRED is not set
# CONFIG_EXT_API_PROVIDE_EXT_API_ENABLED is not set
# CONFIG_PPI_TRACE is not set
# CONFIG_CPU_LOAD is not set

#
# Nordic MPSL
#
CONFIG_MPSL_THREAD_COOP_PRIO=8
CONFIG_MPSL_SIGNAL_STACK_SIZE=1024
CONFIG_MPSL_TIMESLOT_SESSION_COUNT=0
# CONFIG_MPSL_LOG_LEVEL_OFF is not set
# CONFIG_MPSL_LOG_LEVEL_ERR is not set
# CONFIG_MPSL_LOG_LEVEL_WRN is not set
CONFIG_MPSL_LOG_LEVEL_INF=y
# CONFIG_MPSL_LOG_LEVEL_DBG is not set
CONFIG_MPSL_LOG_LEVEL=3
# end of Nordic MPSL

#
# Partition Manager
#
CONFIG_PARTITION_MANAGER_ENABLED=y
CONFIG_SRAM_SIZE=128
CONFIG_SRAM_BASE_ADDRESS=0x20020000

#
# Zephyr subsystem configurations
#
# end of Zephyr subsystem configurations

#
# Zephyr samples configurations
#
# end of Zephyr samples configurations

#
# NCS subsystem configurations
#

#
# NCS samples configurations
#
# end of NCS samples configurations

# CONFIG_PM_SINGLE_IMAGE is not set
# CONFIG_PM_EXTERNAL_FLASH is not set
# CONFIG_BUILD_WITH_TFM is not set
CONFIG_PM_SRAM_BASE=0x20000000
CONFIG_PM_SRAM_SIZE=0x40000
# end of Partition Manager

#
# nRF RPC (Remote Procedure Call) library
#
# end of nRF RPC (Remote Procedure Call) library

#
# Full Modem Firmware Update Management(FMFU)
#
# CONFIG_MGMT_FMFU_LOG_LEVEL_OFF is not set
# CONFIG_MGMT_FMFU_LOG_LEVEL_ERR is not set
# CONFIG_MGMT_FMFU_LOG_LEVEL_WRN is not set
CONFIG_MGMT_FMFU_LOG_LEVEL_INF=y
# CONFIG_MGMT_FMFU_LOG_LEVEL_DBG is not set
CONFIG_MGMT_FMFU_LOG_LEVEL=3
# end of Full Modem Firmware Update Management(FMFU)

CONFIG_SIGN_IMAGES=y
CONFIG_TFM_BOARD="/home/ismail/hub/nrf/modules/tfm/boards/nrf9160"
# CONFIG_CDDL_GEN is not set

#
# Libraries
#
# CONFIG_AGPS is not set
# CONFIG_AGPS_LOG_LEVEL_OFF is not set
# CONFIG_AGPS_LOG_LEVEL_ERR is not set
# CONFIG_AGPS_LOG_LEVEL_WRN is not set
CONFIG_AGPS_LOG_LEVEL_INF=y
# CONFIG_AGPS_LOG_LEVEL_DBG is not set
CONFIG_AGPS_LOG_LEVEL=3

#
# Binary libraries
#
# end of Binary libraries

CONFIG_NRF_MODEM_LIB=y
# CONFIG_NRF_MODEM_LIB_SYS_INIT is not set
# CONFIG_NRF_MODEM_LIB_TRACE_ENABLED is not set
# CONFIG_NRF91_SOCKET_SEND_SPLIT_LARGE_BLOCKS is not set
CONFIG_NRF91_SOCKET_BLOCK_LIMIT=2048
CONFIG_NRF_MODEM_LIB_SENDMSG_BUF_SIZE=128

#
# Heap and buffers
#
CONFIG_NRF_MODEM_LIB_HEAP_SIZE=512
CONFIG_NRF_MODEM_LIB_SHMEM_CTRL_SIZE=0x4e8
CONFIG_NRF_MODEM_LIB_SHMEM_TX_SIZE=8192
CONFIG_NRF_MODEM_LIB_SHMEM_RX_SIZE=8192
CONFIG_NRF_MODEM_LIB_SHMEM_TRACE_SIZE=0

#
# Diagnostics
#
# CONFIG_NRF_MODEM_LIB_DEBUG_ALLOC is not set
# CONFIG_NRF_MODEM_LIB_DEBUG_SHM_TX_ALLOC is not set
# CONFIG_NRF_MODEM_LIB_HEAP_DUMP_PERIODIC is not set
# CONFIG_NRF_MODEM_LIB_SHM_TX_DUMP_PERIODIC is not set
# end of Diagnostics

# CONFIG_NRF_MODEM_LIB_LOG_LEVEL_OFF is not set
# CONFIG_NRF_MODEM_LIB_LOG_LEVEL_ERR is not set
# CONFIG_NRF_MODEM_LIB_LOG_LEVEL_WRN is not set
CONFIG_NRF_MODEM_LIB_LOG_LEVEL_INF=y
# CONFIG_NRF_MODEM_LIB_LOG_LEVEL_DBG is not set
CONFIG_NRF_MODEM_LIB_LOG_LEVEL=3

#
# BSD library (deprecated)
#

#
# All the configs below are deprecated, please use NRF_MODEM_LIB equivalents instead
#
# CONFIG_BSD_LIBRARY is not set
# end of BSD library (deprecated)

# CONFIG_ADP536X is not set

#
# AT Command driver
#
CONFIG_AT_CMD=y
# CONFIG_AT_CMD_SYS_INIT is not set
CONFIG_AT_CMD_THREAD_PRIO=10
CONFIG_AT_CMD_THREAD_STACK_SIZE=1024
CONFIG_AT_CMD_QUEUE_LEN=16
CONFIG_AT_CMD_RESPONSE_MAX_LEN=2700
# CONFIG_AT_CMD_LOG_LEVEL_OFF is not set
# CONFIG_AT_CMD_LOG_LEVEL_ERR is not set
# CONFIG_AT_CMD_LOG_LEVEL_WRN is not set
CONFIG_AT_CMD_LOG_LEVEL_INF=y
# CONFIG_AT_CMD_LOG_LEVEL_DBG is not set
CONFIG_AT_CMD_LOG_LEVEL=3
# end of AT Command driver

CONFIG_LTE_LINK_CONTROL=y
# CONFIG_LTE_AUTO_INIT_AND_CONNECT is not set
# CONFIG_LTE_LOCK_BANDS is not set
# CONFIG_LTE_LOCK_PLMN is not set
# CONFIG_LTE_UNLOCK_PLMN is not set
CONFIG_LTE_PSM_REQ_RPTAU="00000011"
CONFIG_LTE_PSM_REQ_RAT="00100001"
# CONFIG_LTE_EDRX_REQ is not set
CONFIG_LTE_EDRX_REQ_VALUE="1001"
CONFIG_LTE_PTW_VALUE=""
# CONFIG_LTE_LEGACY_PCO_MODE is not set
# CONFIG_LTE_PDP_CMD is not set
# CONFIG_LTE_PDN_AUTH_CMD is not set
CONFIG_LTE_NETWORK_MODE_LTE_M=y
# CONFIG_LTE_NETWORK_MODE_LTE_M_GPS is not set
# CONFIG_LTE_NETWORK_MODE_NBIOT is not set
# CONFIG_LTE_NETWORK_MODE_NBIOT_GPS is not set
CONFIG_LTE_RAI_REQ_VALUE="0"
CONFIG_LTE_NETWORK_USE_FALLBACK=y
CONFIG_LTE_NETWORK_TIMEOUT=600
# CONFIG_LTE_LINK_CONTROL_LOG_LEVEL_OFF is not set
# CONFIG_LTE_LINK_CONTROL_LOG_LEVEL_ERR is not set
# CONFIG_LTE_LINK_CONTROL_LOG_LEVEL_WRN is not set
CONFIG_LTE_LINK_CONTROL_LOG_LEVEL_INF=y
# CONFIG_LTE_LINK_CONTROL_LOG_LEVEL_DBG is not set
CONFIG_LTE_LINK_CONTROL_LOG_LEVEL=3
# CONFIG_FPROTECT is not set
CONFIG_NRF_SPU_FLASH_REGION_SIZE=0x8000
CONFIG_FPROTECT_BLOCK_SIZE=0x8000
CONFIG_AT_NOTIF=y
# CONFIG_AT_NOTIF_SYS_INIT is not set
# CONFIG_AT_NOTIF_LOG_LEVEL_OFF is not set
# CONFIG_AT_NOTIF_LOG_LEVEL_ERR is not set
# CONFIG_AT_NOTIF_LOG_LEVEL_WRN is not set
CONFIG_AT_NOTIF_LOG_LEVEL_INF=y
# CONFIG_AT_NOTIF_LOG_LEVEL_DBG is not set
CONFIG_AT_NOTIF_LOG_LEVEL=3

#
# AT Host Library for nrf91
#
# CONFIG_AT_HOST_LIBRARY is not set
# end of AT Host Library for nrf91

# CONFIG_DK_LIBRARY is not set
CONFIG_AT_CMD_PARSER=y
CONFIG_MODEM_INFO=y
CONFIG_MODEM_INFO_MAX_AT_PARAMS_RSP=10
CONFIG_MODEM_INFO_BUFFER_SIZE=128
CONFIG_MODEM_INFO_ADD_NETWORK=y
CONFIG_MODEM_INFO_ADD_DATE_TIME=y
CONFIG_MODEM_INFO_ADD_SIM=y
CONFIG_MODEM_INFO_ADD_SIM_ICCID=y
CONFIG_MODEM_INFO_ADD_SIM_IMSI=y
CONFIG_MODEM_INFO_ADD_DEVICE=y
CONFIG_MODEM_INFO_ADD_BOARD=y
# CONFIG_PDN_MANAGEMENT is not set
CONFIG_RESET_ON_FATAL_ERROR=y
# CONFIG_FATAL_ERROR_LOG_LEVEL_OFF is not set
# CONFIG_FATAL_ERROR_LOG_LEVEL_ERR is not set
# CONFIG_FATAL_ERROR_LOG_LEVEL_WRN is not set
CONFIG_FATAL_ERROR_LOG_LEVEL_INF=y
# CONFIG_FATAL_ERROR_LOG_LEVEL_DBG is not set
CONFIG_FATAL_ERROR_LOG_LEVEL=3
# CONFIG_SMS is not set
CONFIG_MODEM_KEY_MGMT=y
# CONFIG_MODEM_KEY_MGMT_LOG_LEVEL_OFF is not set
# CONFIG_MODEM_KEY_MGMT_LOG_LEVEL_ERR is not set
# CONFIG_MODEM_KEY_MGMT_LOG_LEVEL_WRN is not set
CONFIG_MODEM_KEY_MGMT_LOG_LEVEL_INF=y
# CONFIG_MODEM_KEY_MGMT_LOG_LEVEL_DBG is not set
CONFIG_MODEM_KEY_MGMT_LOG_LEVEL=3
# CONFIG_SUPL_CLIENT_LIB is not set
# CONFIG_DATE_TIME is not set
# CONFIG_RAM_POWER_DOWN_LIBRARY is not set
# end of Libraries

#
# Device Drivers
#
# CONFIG_BT_DRIVER_QUIRK_NO_AUTO_DLE is not set
CONFIG_ENTROPY_CC3XX=y
# CONFIG_ETH_RTT is not set
# CONFIG_SENSOR is not set

#
# GPS Drivers
#
# CONFIG_GPS_SIM is not set
# CONFIG_NRF9160_GPS is not set
# end of GPS Drivers

# CONFIG_NRF_SW_LPUART is not set
# end of Device Drivers

#
# External libraries
#
# CONFIG_CJSON_LIB is not set
# end of External libraries

# CONFIG_UNITY is not set
# end of Nordic nRF Connect

CONFIG_ZEPHYR_NRF_MODULE=y
# end of nrf (/home/ismail/hub/nrf)

#
# mcuboot (/home/ismail/hub/bootloader/mcuboot)
#

#
# MCUboot
#
# CONFIG_MCUBOOT_BUILD_STRATEGY_USE_HEX_FILE is not set
# CONFIG_MCUBOOT_BUILD_STRATEGY_SKIP_BUILD is not set
CONFIG_MCUBOOT_BUILD_STRATEGY_FROM_SOURCE=y
CONFIG_MCUBOOT_IMAGE_VERSION="1.0.8"
CONFIG_MCUBOOT_FLASH_WRITE_BLOCK_SIZE=4
CONFIG_DT_FLASH_WRITE_BLOCK_SIZE=4
# end of MCUboot

CONFIG_ZEPHYR_MCUBOOT_MODULE=y
# end of mcuboot (/home/ismail/hub/bootloader/mcuboot)

#
# nrfxlib (/home/ismail/hub/nrfxlib)
#

#
# Nordic nrfxlib
#
CONFIG_NRF_MODEM=y
CONFIG_NRF_MODEM_LINK_BINARY=y
CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE=0x4e8
# CONFIG_NFC_T2T_NRFXLIB is not set
# CONFIG_NFC_T4T_NRFXLIB is not set

#
# Crypto libraries for nRF5x SOCs.
#
# CONFIG_NRF_OBERON is not set
# CONFIG_NRF_CC310_BL is not set
# end of Crypto libraries for nRF5x SOCs.

#
# Nordic Security
#
# CONFIG_NORDIC_SECURITY_BACKEND is not set
# end of Nordic Security

# CONFIG_NRF_RPC is not set

#
# ZBOSS library configuration
#
CONFIG_ZIGBEE_LIBRARY_DEVELOPMENT=y
CONFIG_ZIGBEE_LIBRARY_SOC=y
# CONFIG_ZIGBEE_LIBRARY_NCP_DEV is not set
# CONFIG_ZIGBEE_GP_NONE is not set
CONFIG_ZIGBEE_GP_PB=y
# CONFIG_ZIGBEE_GP_CB is not set
# end of ZBOSS library configuration
# end of Nordic nrfxlib

CONFIG_ZEPHYR_NRFXLIB_MODULE=y
# end of nrfxlib (/home/ismail/hub/nrfxlib)

#
# hal_nordic (/home/ismail/hub/modules/hal/nordic)
#
CONFIG_ZEPHYR_HAL_NORDIC_MODULE=y
CONFIG_HAS_NRFX=y

#
# nrfx drivers
#
CONFIG_NRFX_CLOCK=y
CONFIG_NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED=y
CONFIG_NRFX_DPPI=y
# CONFIG_NRFX_EGU is not set
# CONFIG_NRFX_EGU0 is not set
# CONFIG_NRFX_EGU1 is not set
# CONFIG_NRFX_EGU2 is not set
# CONFIG_NRFX_EGU3 is not set
# CONFIG_NRFX_EGU4 is not set
# CONFIG_NRFX_EGU5 is not set
CONFIG_NRFX_GPIOTE=y
# CONFIG_NRFX_I2S is not set
CONFIG_NRFX_IPC=y
CONFIG_NRFX_NVMC=y
# CONFIG_NRFX_PDM is not set
# CONFIG_NRFX_POWER is not set
# CONFIG_NRFX_PWM is not set
# CONFIG_NRFX_PWM0 is not set
# CONFIG_NRFX_PWM1 is not set
# CONFIG_NRFX_PWM2 is not set
# CONFIG_NRFX_PWM3 is not set
# CONFIG_NRFX_RTC is not set
# CONFIG_NRFX_RTC0 is not set
# CONFIG_NRFX_RTC1 is not set
# CONFIG_NRFX_SAADC is not set
# CONFIG_NRFX_SPIM is not set
# CONFIG_NRFX_SPIM0 is not set
# CONFIG_NRFX_SPIM1 is not set
# CONFIG_NRFX_SPIM2 is not set
# CONFIG_NRFX_SPIM3 is not set
# CONFIG_NRFX_SPIS is not set
# CONFIG_NRFX_SPIS0 is not set
# CONFIG_NRFX_SPIS1 is not set
# CONFIG_NRFX_SPIS2 is not set
# CONFIG_NRFX_SPIS3 is not set
# CONFIG_NRFX_SYSTICK is not set
# CONFIG_NRFX_TIMER is not set
# CONFIG_NRFX_TIMER0 is not set
# CONFIG_NRFX_TIMER1 is not set
# CONFIG_NRFX_TIMER2 is not set
# CONFIG_NRFX_TWIM is not set
# CONFIG_NRFX_TWIM0 is not set
# CONFIG_NRFX_TWIM1 is not set
# CONFIG_NRFX_TWIM2 is not set
# CONFIG_NRFX_TWIM3 is not set
# CONFIG_NRFX_TWIS is not set
# CONFIG_NRFX_TWIS0 is not set
# CONFIG_NRFX_TWIS1 is not set
# CONFIG_NRFX_TWIS2 is not set
# CONFIG_NRFX_TWIS3 is not set
CONFIG_NRFX_UARTE=y
CONFIG_NRFX_UARTE0=y
# CONFIG_NRFX_UARTE1 is not set
# CONFIG_NRFX_UARTE2 is not set
# CONFIG_NRFX_UARTE3 is not set
# CONFIG_NRFX_WDT is not set
# CONFIG_NRFX_WDT0 is not set
# CONFIG_NRFX_PRS is not set
# CONFIG_NRFX_PRS_BOX_0 is not set
# CONFIG_NRFX_PRS_BOX_1 is not set
# CONFIG_NRFX_PRS_BOX_2 is not set
# CONFIG_NRFX_PRS_BOX_3 is not set
# CONFIG_NRFX_PRS_BOX_4 is not set
# end of nrfx drivers
# end of hal_nordic (/home/ismail/hub/modules/hal/nordic)

#
# cddl-gen (/home/ismail/hub/modules/lib/cddl-gen)
#
CONFIG_ZEPHYR_CDDL_GEN_MODULE=y
# end of cddl-gen (/home/ismail/hub/modules/lib/cddl-gen)

#
# connectedhomeip (/home/ismail/hub/modules/lib/connectedhomeip)
#
# CONFIG_CHIP is not set
CONFIG_ZEPHYR_CONNECTEDHOMEIP_MODULE=y
# end of connectedhomeip (/home/ismail/hub/modules/lib/connectedhomeip)

#
# Optional modules. Make sure they're installed, via the project manifest.
#
# CONFIG_CANOPENNODE is not set
# CONFIG_CIVETWEB is not set
CONFIG_HAS_CMSIS_CORE=y
CONFIG_HAS_CMSIS_CORE_M=y
# CONFIG_CMSIS_DSP is not set
# CONFIG_LIBMETAL is not set
# CONFIG_HAS_SEMTECH_LORAMAC is not set
# CONFIG_HAS_SEMTECH_SOFT_SE is not set
# CONFIG_HAS_SEMTECH_RADIO_DRIVERS is not set
# CONFIG_MBEDTLS is not set
# CONFIG_HAS_MEC_HAL is not set
# CONFIG_OPENAMP is not set
# CONFIG_SOF is not set
# CONFIG_MIPI_SYST_LIB is not set
CONFIG_NUM_PREEMPT_PRIORITIES=15
CONFIG_TINYCBOR=y
# CONFIG_CBOR_ENCODER_NO_CHECK_USER is not set
CONFIG_CBOR_PARSER_MAX_RECURSIONS=1024
# CONFIG_CBOR_PARSER_NO_STRICT_CHECKS is not set
# CONFIG_CBOR_FLOATING_POINT is not set
# CONFIG_CBOR_HALF_FLOAT_TYPE is not set
CONFIG_CBOR_WITHOUT_OPEN_MEMSTREAM=y
# CONFIG_CBOR_PRETTY_PRINTING is not set
CONFIG_MCUBOOT_BOOTUTIL_LIB=y
CONFIG_MCUBOOT_BOOTUTIL_LIB_OWN_LOG=y
# CONFIG_MCUBOOT_UTIL_LOG_LEVEL_OFF is not set
# CONFIG_MCUBOOT_UTIL_LOG_LEVEL_ERR is not set
# CONFIG_MCUBOOT_UTIL_LOG_LEVEL_WRN is not set
CONFIG_MCUBOOT_UTIL_LOG_LEVEL_INF=y
# CONFIG_MCUBOOT_UTIL_LOG_LEVEL_DBG is not set
CONFIG_MCUBOOT_UTIL_LOG_LEVEL=3

#
# Unavailable modules, please install those via the project manifest.
#
# end of Modules

# CONFIG_BOARD_TINYCARRIER_NRF9160 is not set
CONFIG_BOARD_TINYCARRIER_NRF9160NS=y

#
# Board Options
#
# end of Board Options

# CONFIG_SOC_SERIES_BEETLE is not set
# CONFIG_SOC_SERIES_ARM_DESIGNSTART is not set
# CONFIG_SOC_SERIES_MPS2 is not set
# CONFIG_SOC_SERIES_MUSCA is not set
# CONFIG_SOC_SERIES_MUSCA_B1 is not set
# CONFIG_SOC_SERIES_MUSCA_S1 is not set
# CONFIG_SOC_SERIES_SAM3X is not set
# CONFIG_SOC_SERIES_SAM4E is not set
# CONFIG_SOC_SERIES_SAM4L is not set
# CONFIG_SOC_SERIES_SAM4S is not set
# CONFIG_SOC_SERIES_SAME70 is not set
# CONFIG_SOC_SERIES_SAMV71 is not set
# CONFIG_SOC_SERIES_SAMD20 is not set
# CONFIG_SOC_SERIES_SAMD21 is not set
# CONFIG_SOC_SERIES_SAMD51 is not set
# CONFIG_SOC_SERIES_SAME51 is not set
# CONFIG_SOC_SERIES_SAME53 is not set
# CONFIG_SOC_SERIES_SAME54 is not set
# CONFIG_SOC_SERIES_SAMR21 is not set
# CONFIG_SOC_SERIES_VALKYRIE is not set
# CONFIG_SOC_SERIES_VIPER is not set
# CONFIG_SOC_SERIES_PSOC62 is not set
# CONFIG_SOC_SERIES_PSOC63 is not set
# CONFIG_SOC_SERIES_XMC_4XXX is not set
# CONFIG_SOC_SERIES_MEC1501X is not set
# CONFIG_SOC_SERIES_MEC1701X is not set
# CONFIG_SOC_SERIES_NRF51X is not set
# CONFIG_SOC_SERIES_NRF52X is not set
# CONFIG_SOC_SERIES_NRF53X is not set
CONFIG_SOC_SERIES_NRF91X=y
# CONFIG_SOC_SERIES_M48X is not set
# CONFIG_SOC_SERIES_NPCX7 is not set
# CONFIG_SOC_SERIES_IMX_6X_M4 is not set
# CONFIG_SOC_SERIES_IMX7_M4 is not set
# CONFIG_SOC_SERIES_IMX8MM_M4 is not set
# CONFIG_SOC_SERIES_IMX_RT is not set
# CONFIG_SOC_SERIES_IMX_RT6XX is not set
# CONFIG_SOC_SERIES_KINETIS_K2X is not set
# CONFIG_SOC_SERIES_KINETIS_K6X is not set
# CONFIG_SOC_SERIES_KINETIS_K8X is not set
# CONFIG_SOC_SERIES_KINETIS_KE1XF is not set
# CONFIG_SOC_SERIES_KINETIS_KL2X is not set
# CONFIG_SOC_SERIES_KINETIS_KV5X is not set
# CONFIG_SOC_SERIES_KINETIS_KWX is not set
# CONFIG_SOC_SERIES_LPC11U6X is not set
# CONFIG_SOC_SERIES_LPC54XXX is not set
# CONFIG_SOC_SERIES_LPC55XXX is not set
# CONFIG_SOC_QEMU_CORTEX_A53 is not set
# CONFIG_SOC_EOS_S3 is not set
# CONFIG_SOC_SERIES_EFM32GG11B is not set
# CONFIG_SOC_SERIES_EFM32HG is not set
# CONFIG_SOC_SERIES_EFM32JG12B is not set
# CONFIG_SOC_SERIES_EFM32PG12B is not set
# CONFIG_SOC_SERIES_EFM32PG1B is not set
# CONFIG_SOC_SERIES_EFM32WG is not set
# CONFIG_SOC_SERIES_EFR32BG13P is not set
# CONFIG_SOC_SERIES_EFR32FG1P is not set
# CONFIG_SOC_SERIES_EFR32MG12P is not set
# CONFIG_SOC_SERIES_EFR32MG21 is not set
# CONFIG_SOC_SERIES_STM32F0X is not set
# CONFIG_SOC_SERIES_STM32F1X is not set
# CONFIG_SOC_SERIES_STM32F2X is not set
# CONFIG_SOC_SERIES_STM32F3X is not set
# CONFIG_SOC_SERIES_STM32F4X is not set
# CONFIG_SOC_SERIES_STM32F7X is not set
# CONFIG_SOC_SERIES_STM32G0X is not set
# CONFIG_SOC_SERIES_STM32G4X is not set
# CONFIG_SOC_SERIES_STM32H7X is not set
# CONFIG_SOC_SERIES_STM32L0X is not set
# CONFIG_SOC_SERIES_STM32L1X is not set
# CONFIG_SOC_SERIES_STM32L4X is not set
# CONFIG_SOC_SERIES_STM32L5X is not set
# CONFIG_SOC_SERIES_STM32MP1X is not set
# CONFIG_SOC_SERIES_STM32WBX is not set
# CONFIG_SOC_TI_LM3S6965 is not set
# CONFIG_SOC_SERIES_CC13X2_CC26X2 is not set
# CONFIG_SOC_SERIES_CC32XX is not set
# CONFIG_SOC_SERIES_MSP432P4XX is not set
# CONFIG_SOC_XILINX_ZYNQMP_RPU is not set

#
# Hardware Configuration
#
CONFIG_CPU_HAS_ARM_MPU=y
CONFIG_CPU_HAS_NRF_IDAU=y
CONFIG_NRF_SPU_RAM_REGION_SIZE=0x2000
CONFIG_SOC_FAMILY="nordic_nrf"
CONFIG_SOC_FAMILY_NRF=y
CONFIG_HAS_HW_NRF_CC310=y
CONFIG_HAS_HW_NRF_CLOCK=y
CONFIG_HAS_HW_NRF_DPPIC=y
CONFIG_HAS_HW_NRF_EGU0=y
CONFIG_HAS_HW_NRF_EGU1=y
CONFIG_HAS_HW_NRF_EGU2=y
CONFIG_HAS_HW_NRF_EGU3=y
CONFIG_HAS_HW_NRF_EGU4=y
CONFIG_HAS_HW_NRF_EGU5=y
CONFIG_HAS_HW_NRF_GPIO0=y
CONFIG_HAS_HW_NRF_GPIOTE=y
CONFIG_HAS_HW_NRF_I2S=y
CONFIG_HAS_HW_NRF_IPC=y
CONFIG_HAS_HW_NRF_NVMC_PE=y
CONFIG_HAS_HW_NRF_PDM=y
CONFIG_HAS_HW_NRF_POWER=y
CONFIG_HAS_HW_NRF_PWM0=y
CONFIG_HAS_HW_NRF_PWM1=y
CONFIG_HAS_HW_NRF_PWM2=y
CONFIG_HAS_HW_NRF_PWM3=y
CONFIG_HAS_HW_NRF_RTC0=y
CONFIG_HAS_HW_NRF_RTC1=y
CONFIG_HAS_HW_NRF_SAADC=y
CONFIG_HAS_HW_NRF_SPIM0=y
CONFIG_HAS_HW_NRF_SPIM1=y
CONFIG_HAS_HW_NRF_SPIM2=y
CONFIG_HAS_HW_NRF_SPIM3=y
CONFIG_HAS_HW_NRF_SPIS0=y
CONFIG_HAS_HW_NRF_SPIS1=y
CONFIG_HAS_HW_NRF_SPIS2=y
CONFIG_HAS_HW_NRF_SPIS3=y
CONFIG_HAS_HW_NRF_SPU=y
CONFIG_HAS_HW_NRF_TIMER0=y
CONFIG_HAS_HW_NRF_TIMER1=y
CONFIG_HAS_HW_NRF_TIMER2=y
CONFIG_HAS_HW_NRF_TWIM0=y
CONFIG_HAS_HW_NRF_TWIM1=y
CONFIG_HAS_HW_NRF_TWIM2=y
CONFIG_HAS_HW_NRF_TWIM3=y
CONFIG_HAS_HW_NRF_TWIS0=y
CONFIG_HAS_HW_NRF_TWIS1=y
CONFIG_HAS_HW_NRF_TWIS2=y
CONFIG_HAS_HW_NRF_TWIS3=y
CONFIG_HAS_HW_NRF_UARTE0=y
CONFIG_HAS_HW_NRF_UARTE1=y
CONFIG_HAS_HW_NRF_UARTE2=y
CONFIG_HAS_HW_NRF_UARTE3=y
CONFIG_HAS_HW_NRF_WDT=y
CONFIG_NRF_HW_RTC1_RESERVED=y
# CONFIG_NRF_ENABLE_ICACHE is not set
CONFIG_SOC_NRF9160=y
CONFIG_SOC_NRF9160_SICA=y
# CONFIG_SOC_LOG_LEVEL_OFF is not set
# CONFIG_SOC_LOG_LEVEL_ERR is not set
# CONFIG_SOC_LOG_LEVEL_WRN is not set
CONFIG_SOC_LOG_LEVEL_INF=y
# CONFIG_SOC_LOG_LEVEL_DBG is not set
CONFIG_SOC_LOG_LEVEL=3
# end of Hardware Configuration

CONFIG_SOC_COMPATIBLE_NRF=y

#
# ARM Options
#
CONFIG_ARCH="arm"
CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEX_M=y
CONFIG_ISA_THUMB2=y
CONFIG_ASSEMBLER_ISA_THUMB2=y
CONFIG_COMPILER_ISA_THUMB2=y
CONFIG_STACK_ALIGN_DOUBLE_WORD=y
# CONFIG_RUNTIME_NMI is not set
CONFIG_PLATFORM_SPECIFIC_INIT=y
CONFIG_FAULT_DUMP=2
CONFIG_BUILTIN_STACK_GUARD=y
CONFIG_ARM_STACK_PROTECTION=y
CONFIG_ARM_NONSECURE_FIRMWARE=y
CONFIG_FP_HARDABI=y
# CONFIG_FP_SOFTABI is not set
CONFIG_CPU_CORTEX_M33=y
CONFIG_CPU_CORTEX_M_HAS_SYSTICK=y
CONFIG_CPU_CORTEX_M_HAS_DWT=y
CONFIG_CPU_CORTEX_M_HAS_BASEPRI=y
CONFIG_CPU_CORTEX_M_HAS_VTOR=y
CONFIG_CPU_CORTEX_M_HAS_SPLIM=y
CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS=y
CONFIG_CPU_CORTEX_M_HAS_CMSE=y
CONFIG_ARMV7_M_ARMV8_M_MAINLINE=y
CONFIG_ARMV8_M_MAINLINE=y
CONFIG_ARMV8_M_SE=y
CONFIG_ARMV7_M_ARMV8_M_FP=y
CONFIG_ARMV8_M_DSP=y

#
# ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33 options
#
CONFIG_GEN_ISR_TABLES=y
# CONFIG_ZERO_LATENCY_IRQS is not set
# CONFIG_SW_VECTOR_RELAY is not set
# CONFIG_CORTEX_M_DWT is not set
# end of ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33 options

CONFIG_ARM_MPU=y
CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE=32
# CONFIG_MPU_STACK_GUARD is not set
CONFIG_MPU_ALLOW_FLASH_WRITE=y
# CONFIG_CUSTOM_SECTION_ALIGN is not set
CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE=32
CONFIG_ARM_TRUSTZONE_M=y

#
# ARM TrustZone-M Options
#

#
# Non-secure firmware
#
CONFIG_ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS=y
# end of ARM TrustZone-M Options

CONFIG_GEN_IRQ_VECTOR_TABLE=y
CONFIG_IDLE_STACK_SIZE=320
CONFIG_ISR_STACK_SIZE=8192
CONFIG_TEST_EXTRA_STACKSIZE=0
# end of ARM Options

CONFIG_ARM=y
CONFIG_ARCH_IS_SET=y

#
# General Architecture Options
#
# CONFIG_ARCH_LOG_LEVEL_OFF is not set
# CONFIG_ARCH_LOG_LEVEL_ERR is not set
# CONFIG_ARCH_LOG_LEVEL_WRN is not set
CONFIG_ARCH_LOG_LEVEL_INF=y
# CONFIG_ARCH_LOG_LEVEL_DBG is not set
CONFIG_ARCH_LOG_LEVEL=3
# CONFIG_MPU_LOG_LEVEL_OFF is not set
# CONFIG_MPU_LOG_LEVEL_ERR is not set
# CONFIG_MPU_LOG_LEVEL_WRN is not set
CONFIG_MPU_LOG_LEVEL_INF=y
# CONFIG_MPU_LOG_LEVEL_DBG is not set
CONFIG_MPU_LOG_LEVEL=3
# CONFIG_TRUSTED_EXECUTION_SECURE is not set
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
CONFIG_HW_STACK_PROTECTION=y
# CONFIG_USERSPACE is not set
CONFIG_KOBJECT_TEXT_AREA=256
CONFIG_GEN_PRIV_STACKS=y
# CONFIG_STACK_GROWS_UP is not set

#
# Interrupt Configuration
#
# CONFIG_DYNAMIC_INTERRUPTS is not set
CONFIG_GEN_SW_ISR_TABLE=y
CONFIG_ARCH_SW_ISR_TABLE_ALIGN=0
CONFIG_GEN_IRQ_START_VECTOR=0
# CONFIG_EXTRA_EXCEPTION_INFO is not set
# end of Interrupt Configuration

CONFIG_INIT_ARCH_HW_AT_BOOT=y
# end of General Architecture Options

CONFIG_ARCH_HAS_TIMING_FUNCTIONS=y
CONFIG_ARCH_HAS_TRUSTED_EXECUTION=y
CONFIG_ARCH_HAS_STACK_PROTECTION=y
CONFIG_ARCH_HAS_USERSPACE=y
CONFIG_ARCH_HAS_EXECUTABLE_PAGE_BIT=y
CONFIG_ARCH_HAS_RAMFUNC_SUPPORT=y
CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION=y
CONFIG_ARCH_SUPPORTS_COREDUMP=y
CONFIG_ARCH_SUPPORTS_ARCH_HW_INIT=y
CONFIG_ARCH_HAS_EXTRA_EXCEPTION_INFO=y
CONFIG_ARCH_HAS_THREAD_LOCAL_STORAGE=y
CONFIG_ARCH_HAS_THREAD_ABORT=y
CONFIG_CPU_HAS_TEE=y
CONFIG_CPU_HAS_FPU=y
CONFIG_CPU_HAS_MPU=y
CONFIG_MPU=y
CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS=y
CONFIG_MPU_GAP_FILLING=y
CONFIG_SRAM_REGION_PERMISSIONS=y

#
# Floating Point Options
#
CONFIG_FPU_SHARING=y
# end of Floating Point Options

#
# Cache Options
#
# CONFIG_CACHE_MANAGEMENT is not set
# end of Cache Options

#
# General Kernel Options
#
# CONFIG_KERNEL_LOG_LEVEL_OFF is not set
# CONFIG_KERNEL_LOG_LEVEL_ERR is not set
# CONFIG_KERNEL_LOG_LEVEL_WRN is not set
CONFIG_KERNEL_LOG_LEVEL_INF=y
# CONFIG_KERNEL_LOG_LEVEL_DBG is not set
CONFIG_KERNEL_LOG_LEVEL=3
CONFIG_MULTITHREADING=y
CONFIG_NUM_COOP_PRIORITIES=16
CONFIG_MAIN_THREAD_PRIORITY=0
CONFIG_COOP_ENABLED=y
CONFIG_PREEMPT_ENABLED=y
CONFIG_PRIORITY_CEILING=0
CONFIG_NUM_METAIRQ_PRIORITIES=0
# CONFIG_SCHED_DEADLINE is not set
# CONFIG_SCHED_CPU_MASK is not set
CONFIG_THREAD_STACK_INFO=y
# CONFIG_THREAD_CUSTOM_DATA is not set
CONFIG_ERRNO=y
CONFIG_SCHED_DUMB=y
# CONFIG_SCHED_SCALABLE is not set
# CONFIG_SCHED_MULTIQ is not set
# CONFIG_WAITQ_SCALABLE is not set
CONFIG_WAITQ_DUMB=y

#
# Kernel Debugging and Metrics
#
# CONFIG_INIT_STACKS is not set
CONFIG_BOOT_DELAY=0
CONFIG_THREAD_MONITOR=y
# CONFIG_THREAD_NAME is not set
# CONFIG_THREAD_RUNTIME_STATS is not set
# end of Kernel Debugging and Metrics

#
# Work Queue Options
#
CONFIG_SYSTEM_WORKQUEUE_PRIORITY=-1
# end of Work Queue Options

#
# Atomic Operations
#
CONFIG_ATOMIC_OPERATIONS_BUILTIN=y
# end of Atomic Operations

#
# Timer API Options
#
CONFIG_TIMESLICING=y
CONFIG_TIMESLICE_SIZE=0
CONFIG_TIMESLICE_PRIORITY=0
CONFIG_POLL=y
# end of Timer API Options

#
# Other Kernel Object Options
#
# CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION is not set
CONFIG_NUM_MBOX_ASYNC_MSGS=10
CONFIG_NUM_PIPE_ASYNC_MSGS=10
CONFIG_KERNEL_MEM_POOL=y
# end of Other Kernel Object Options

CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN=y
CONFIG_SWAP_NONATOMIC=y
CONFIG_SYS_CLOCK_EXISTS=y
CONFIG_TIMEOUT_64BIT=y
CONFIG_XIP=y

#
# Initialization Priorities
#
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS=30
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT=40
CONFIG_KERNEL_INIT_PRIORITY_DEVICE=50
CONFIG_APPLICATION_INIT_PRIORITY=90
# end of Initialization Priorities

#
# Security Options
#
# CONFIG_STACK_CANARIES is not set
CONFIG_STACK_POINTER_RANDOM=0
# end of Security Options

#
# SMP Options
#
CONFIG_MP_NUM_CPUS=1
# end of SMP Options

CONFIG_TICKLESS_IDLE=y
CONFIG_TICKLESS_IDLE_THRESH=3
CONFIG_TICKLESS_KERNEL=y
CONFIG_TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE=y
# CONFIG_THREAD_LOCAL_STORAGE is not set
# end of General Kernel Options

CONFIG_HAS_DTS=y
CONFIG_HAS_DTS_GPIO=y

#
# Device Drivers
#
# CONFIG_IEEE802154 is not set
# CONFIG_LORA is not set
# CONFIG_CONSOLE is not set
CONFIG_HAS_SEGGER_RTT=y
# CONFIG_USE_SEGGER_RTT is not set
# CONFIG_EC_HOST_CMD_PERIPH is not set
# CONFIG_NET_LOOPBACK is not set

#
# Capabilities
#
CONFIG_SERIAL_HAS_DRIVER=y
CONFIG_SERIAL_SUPPORT_ASYNC=y
CONFIG_SERIAL_SUPPORT_INTERRUPT=y
CONFIG_UART_ASYNC_API=y
# CONFIG_UART_LINE_CTRL is not set
# CONFIG_UART_DRV_CMD is not set

#
# Serial Drivers
#
CONFIG_UART_NRFX=y
CONFIG_UART_0_NRF_UARTE=y
CONFIG_UART_0_ENHANCED_POLL_OUT=y
CONFIG_UART_0_ASYNC=y
# CONFIG_UART_0_NRF_PARITY_BIT is not set
CONFIG_UART_0_NRF_TX_BUFFER_SIZE=32
# CONFIG_UART_0_NRF_HW_ASYNC is not set
CONFIG_UART_1_NRF_UARTE=y
CONFIG_UART_1_ASYNC=y
CONFIG_UART_1_ENHANCED_POLL_OUT=y
# CONFIG_UART_1_NRF_PARITY_BIT is not set
# CONFIG_UART_1_NRF_HW_ASYNC is not set
CONFIG_NRF_UARTE_PERIPHERAL=y
# CONFIG_UART_ALTERA_JTAG is not set
# CONFIG_UART_XLNX_UARTLITE is not set

#
# Interrupt Controllers
#
# CONFIG_SWERV_PIC is not set
# CONFIG_MULTI_LEVEL_INTERRUPTS is not set
# end of Interrupt Controllers

#
# Timer Drivers
#
CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT=0
# CONFIG_SYSTEM_CLOCK_NO_WAIT is not set
# CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY is not set
CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY=y
CONFIG_SYSTEM_CLOCK_DISABLE=y
# CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME is not set
# CONFIG_SYSTEM_CLOCK_SLOPPY_IDLE is not set
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY=0
CONFIG_TICKLESS_CAPABLE=y
# end of Timer Drivers

CONFIG_ENTROPY_GENERATOR=y
CONFIG_ENTROPY_HAS_DRIVER=y
# CONFIG_PCIE is not set
# CONFIG_PCIE_ENDPOINT is not set
# CONFIG_GPIO_LOG_LEVEL_OFF is not set
# CONFIG_GPIO_LOG_LEVEL_ERR is not set
# CONFIG_GPIO_LOG_LEVEL_WRN is not set
CONFIG_GPIO_LOG_LEVEL_INF=y
# CONFIG_GPIO_LOG_LEVEL_DBG is not set
CONFIG_GPIO_LOG_LEVEL=3
# CONFIG_GPIO_DW is not set
CONFIG_GPIO_NRFX=y
CONFIG_GPIO_NRF_INIT_PRIORITY=40
CONFIG_GPIO_NRF_P0=y
# CONFIG_GPIO_ITE_IT8XXX2 is not set
# CONFIG_GPIO_INTEL_APL is not set
# CONFIG_GPIO_XLNX_AXI is not set
# CONFIG_GPIO_EMUL is not set
# CONFIG_SHARED_IRQ is not set
# CONFIG_I2S is not set
# CONFIG_PWM is not set
# CONFIG_PINMUX is not set
# CONFIG_ADC is not set
# CONFIG_DAC is not set
# CONFIG_CLOCK_CONTROL_LOG_LEVEL_OFF is not set
# CONFIG_CLOCK_CONTROL_LOG_LEVEL_ERR is not set
# CONFIG_CLOCK_CONTROL_LOG_LEVEL_WRN is not set
CONFIG_CLOCK_CONTROL_LOG_LEVEL_INF=y
# CONFIG_CLOCK_CONTROL_LOG_LEVEL_DBG is not set
CONFIG_CLOCK_CONTROL_LOG_LEVEL=3
CONFIG_CLOCK_CONTROL_NRF=y
# CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC is not set
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y
# CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM is not set
# CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM is not set
# CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM is not set
# CONFIG_CLOCK_CONTROL_NRF_K32SRC_100PPM is not set
# CONFIG_CLOCK_CONTROL_NRF_K32SRC_75PPM is not set
# CONFIG_CLOCK_CONTROL_NRF_K32SRC_50PPM is not set
# CONFIG_CLOCK_CONTROL_NRF_K32SRC_30PPM is not set
CONFIG_CLOCK_CONTROL_NRF_K32SRC_20PPM=y
CONFIG_CLOCK_CONTROL_NRF_ACCURACY=20
# CONFIG_PTP_CLOCK is not set
# CONFIG_IPM is not set
CONFIG_FLASH_HAS_DRIVER_ENABLED=y
CONFIG_FLASH_HAS_PAGE_LAYOUT=y
CONFIG_FLASH=y
# CONFIG_FLASH_LOG_LEVEL_OFF is not set
# CONFIG_FLASH_LOG_LEVEL_ERR is not set
# CONFIG_FLASH_LOG_LEVEL_WRN is not set
CONFIG_FLASH_LOG_LEVEL_INF=y
# CONFIG_FLASH_LOG_LEVEL_DBG is not set
CONFIG_FLASH_LOG_LEVEL=3
CONFIG_FLASH_PAGE_LAYOUT=y
CONFIG_SOC_FLASH_NRF=y
CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE=y
# CONFIG_SOC_FLASH_NRF_PARTIAL_ERASE is not set
# CONFIG_SOC_FLASH_NRF_EMULATE_ONE_BYTE_WRITE_ACCESS is not set
# CONFIG_FLASH_SIMULATOR is not set
# CONFIG_COUNTER is not set
# CONFIG_DMA is not set
# CONFIG_USB is not set
# CONFIG_CRYPTO is not set
# CONFIG_DISPLAY is not set
# CONFIG_LED_STRIP is not set
# CONFIG_LED is not set
# CONFIG_CAN is not set
# CONFIG_AUDIO is not set
# CONFIG_NEURAL_NET_ACCEL is not set
CONFIG_HWINFO=y
# CONFIG_ESPI is not set
# CONFIG_PS2 is not set
# CONFIG_VIDEO is not set
# CONFIG_EEPROM is not set
# CONFIG_PECI is not set
# CONFIG_PECI_INTERRUPT_DRIVEN is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEMC is not set
# CONFIG_VIRTUALIZATION is not set
# end of Device Drivers

#
# C Library
#
# CONFIG_MINIMAL_LIBC is not set
CONFIG_NEWLIB_LIBC=y
# CONFIG_EXTERNAL_LIBC is not set
CONFIG_HAS_NEWLIB_LIBC_NANO=y
CONFIG_NEWLIB_LIBC_NANO=y
CONFIG_NEWLIB_LIBC_FLOAT_PRINTF=y
# CONFIG_NEWLIB_LIBC_FLOAT_SCANF is not set
# end of C Library

#
# Additional libraries
#
# CONFIG_FNMATCH is not set
# CONFIG_LVGL is not set

#
# OS Support Library
#
# CONFIG_JSON_LIBRARY is not set
# CONFIG_RING_BUFFER is not set
CONFIG_BASE64=y
# CONFIG_SYS_HEAP_VALIDATE is not set
CONFIG_SYS_HEAP_ALLOC_LOOPS=3
# CONFIG_PRINTK64 is not set
# CONFIG_PRINTK_SYNC is not set
CONFIG_CBPRINTF_COMPLETE=y
# CONFIG_CBPRINTF_NANO is not set
CONFIG_CBPRINTF_FULL_INTEGRAL=y
# CONFIG_CBPRINTF_REDUCED_INTEGRAL is not set
CONFIG_CBPRINTF_FP_SUPPORT=y
# CONFIG_CBPRINTF_FP_A_SUPPORT is not set
# CONFIG_CBPRINTF_FP_ALWAYS_A is not set
CONFIG_CBPRINTF_N_SPECIFIER=y
# CONFIG_CBPRINTF_LIBC_SUBSTS is not set
# end of OS Support Library

CONFIG_POSIX_MAX_FDS=4
# CONFIG_POSIX_API is not set
# CONFIG_PTHREAD_IPC is not set
# CONFIG_POSIX_CLOCK is not set
CONFIG_MAX_TIMER_COUNT=5
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_EVENTFD is not set
# CONFIG_OPENAMP_RSC_TABLE is not set
# end of Additional libraries

#
# Sub Systems and OS Services
#
# CONFIG_BT is not set

#
# Controller Area Network (CAN) bus subsystem
#
# CONFIG_ISOTP is not set
# end of Controller Area Network (CAN) bus subsystem

# CONFIG_CONSOLE_SUBSYS is not set
# CONFIG_CPLUSPLUS is not set

#
# System Monitoring Options
#
# CONFIG_BOOT_TIME_MEASUREMENT is not set
# CONFIG_THREAD_ANALYZER is not set
# end of System Monitoring Options

#
# Debugging Options
#
# CONFIG_DEBUG is not set
# CONFIG_STACK_USAGE is not set
# CONFIG_STACK_SENTINEL is not set
CONFIG_PRINTK=y
# CONFIG_EARLY_CONSOLE is not set
CONFIG_ASSERT=y
CONFIG_ASSERT_LEVEL=2
CONFIG_SPIN_VALIDATE=y
# CONFIG_FORCE_NO_ASSERT is not set
CONFIG_ASSERT_VERBOSE=y
# CONFIG_ASSERT_NO_FILE_INFO is not set
# CONFIG_ASSERT_NO_COND_INFO is not set
# CONFIG_ASSERT_NO_MSG_INFO is not set
CONFIG_OBJECT_TRACING=y
# CONFIG_OVERRIDE_FRAME_POINTER_DEFAULT is not set
# CONFIG_DEBUG_INFO is not set
# CONFIG_OPENOCD_SUPPORT is not set
# CONFIG_DEBUG_COREDUMP is not set
# end of Debugging Options

# CONFIG_DISK_ACCESS is not set
# CONFIG_EMUL is not set
# CONFIG_CHARACTER_FRAMEBUFFER is not set

#
# File Systems
#
# CONFIG_FILE_SYSTEM is not set
# CONFIG_FCB is not set
# CONFIG_NVS is not set
# end of File Systems

#
# Inter Processor Communication
#
# CONFIG_RPMSG_SERVICE is not set
# end of Inter Processor Communication

# CONFIG_JWT is not set
CONFIG_LOG=y
# CONFIG_LOG_MINIMAL is not set
# CONFIG_LOG_RUNTIME_FILTERING is not set
CONFIG_LOG_OVERRIDE_LEVEL=0
CONFIG_LOG_MAX_LEVEL=4
# CONFIG_LOG_MIPI_SYST_ENABLE is not set

#
# Prepend non-hexdump log message with function name
#
# CONFIG_LOG_FUNC_NAME_PREFIX_ERR is not set
# CONFIG_LOG_FUNC_NAME_PREFIX_WRN is not set
# CONFIG_LOG_FUNC_NAME_PREFIX_INF is not set
CONFIG_LOG_FUNC_NAME_PREFIX_DBG=y
# end of Prepend non-hexdump log message with function name

CONFIG_LOG_PRINTK=y
CONFIG_LOG_PRINTK_MAX_STRING_LENGTH=128
# CONFIG_LOG_IMMEDIATE is not set
CONFIG_LOG_MODE_OVERFLOW=y
# CONFIG_LOG_MODE_NO_OVERFLOW is not set
# CONFIG_LOG_BLOCK_IN_THREAD is not set
CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD=10
CONFIG_LOG_PROCESS_THREAD=y
CONFIG_LOG_PROCESS_THREAD_SLEEP_MS=1000
CONFIG_LOG_PROCESS_THREAD_STACK_SIZE=8192
CONFIG_LOG_BUFFER_SIZE=1024
CONFIG_LOG_DETECT_MISSED_STRDUP=y
CONFIG_LOG_STRDUP_MAX_STRING=46
CONFIG_LOG_STRDUP_BUF_COUNT=4
# CONFIG_LOG_STRDUP_POOL_PROFILING is not set
CONFIG_LOG_DOMAIN_ID=0
# CONFIG_LOG_FRONTEND is not set
# CONFIG_LOG_BACKEND_NET is not set

#
# Device Management
#

#
# Host command handler subsystem
#
# CONFIG_EC_HOST_CMD is not set
# end of Host command handler subsystem

CONFIG_MCUMGR=y
# CONFIG_MCUMGR_LOG_LEVEL_OFF is not set
# CONFIG_MCUMGR_LOG_LEVEL_ERR is not set
# CONFIG_MCUMGR_LOG_LEVEL_WRN is not set
CONFIG_MCUMGR_LOG_LEVEL_INF=y
# CONFIG_MCUMGR_LOG_LEVEL_DBG is not set
CONFIG_MCUMGR_LOG_LEVEL=3
CONFIG_APP_LINK_WITH_MCUMGR=y
CONFIG_MGMT_CBORATTR_MAX_SIZE=512

#
# Command Handlers
#
CONFIG_MCUMGR_CMD_IMG_MGMT=y
CONFIG_IMG_MGMT_UL_CHUNK_SIZE=512
# CONFIG_IMG_MGMT_VERBOSE_ERR is not set
# CONFIG_IMG_MGMT_DUMMY_HDR is not set
# CONFIG_IMG_MGMT_REJECT_DIRECT_XIP_MISMATCHED_SLOT is not set
# CONFIG_MCUMGR_CMD_OS_MGMT is not set
# end of Command Handlers

# CONFIG_MCUMGR_SMP_BT is not set
# CONFIG_MCUMGR_SMP_SHELL is not set
# CONFIG_MCUMGR_SMP_UART is not set
# CONFIG_MCUMGR_SMP_UDP is not set
CONFIG_MCUMGR_BUF_COUNT=4
CONFIG_MCUMGR_BUF_SIZE=384
CONFIG_MCUMGR_BUF_USER_DATA_SIZE=4
# CONFIG_HAWKBIT is not set
# CONFIG_UPDATEHUB is not set
# CONFIG_OSDP is not set
# end of Device Management

#
# Networking
#
CONFIG_NET_BUF=y
CONFIG_NET_BUF_USER_DATA_SIZE=4
# CONFIG_NET_BUF_LOG is not set
# CONFIG_NET_BUF_LOG_LEVEL_OFF is not set
# CONFIG_NET_BUF_LOG_LEVEL_ERR is not set
# CONFIG_NET_BUF_LOG_LEVEL_WRN is not set
CONFIG_NET_BUF_LOG_LEVEL_INF=y
# CONFIG_NET_BUF_LOG_LEVEL_DBG is not set
CONFIG_NET_BUF_LOG_LEVEL=3
# CONFIG_NET_BUF_POOL_USAGE is not set
CONFIG_NETWORKING=y
# CONFIG_NET_HOSTNAME_ENABLE is not set

#
# Link layer options
#
# CONFIG_NET_L2_DUMMY is not set
# CONFIG_NET_L2_BT_SHELL is not set
# CONFIG_NET_L2_PPP is not set
# CONFIG_NET_L2_OPENTHREAD is not set
# CONFIG_NET_L2_CANBUS_RAW is not set
# CONFIG_NET_L2_ZIGBEE is not set
# CONFIG_NET_L2_WIFI_MGMT is not set
# CONFIG_NET_L2_WIFI_SHELL is not set
# end of Link layer options

#
# IP stack
#
# CONFIG_NET_NATIVE is not set
# CONFIG_NET_OFFLOAD is not set
CONFIG_NET_INIT_PRIO=90
CONFIG_NET_IPV4=y
CONFIG_NET_INITIAL_TTL=64
CONFIG_NET_IF_MAX_IPV4_COUNT=1
CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT=1
CONFIG_NET_IF_MCAST_IPV4_ADDR_COUNT=1
# CONFIG_NET_ICMPV4_ACCEPT_BROADCAST is not set
# CONFIG_NET_IPV4_ACCEPT_ZERO_BROADCAST is not set
# CONFIG_NET_DHCPV4 is not set
# CONFIG_NET_IPV4_HDR_OPTIONS is not set
CONFIG_NET_IPV4_LOG_LEVEL=0
CONFIG_NET_ICMPV4_LOG_LEVEL=0
# CONFIG_NET_SHELL is not set
CONFIG_NET_TC_TX_COUNT=1
CONFIG_NET_TC_RX_COUNT=1
CONFIG_NET_TC_THREAD_COOPERATIVE=y
# CONFIG_NET_TC_THREAD_PREEMPTIVE is not set
CONFIG_NET_TC_NUM_PRIORITIES=16
CONFIG_NET_TC_MAPPING_STRICT=y
CONFIG_NET_TX_DEFAULT_PRIORITY=1
CONFIG_NET_RX_DEFAULT_PRIORITY=0
CONFIG_NET_IP_ADDR_CHECK=y
CONFIG_NET_MAX_ROUTERS=1
CONFIG_NET_TCP=y
CONFIG_NET_TCP_CHECKSUM=y
CONFIG_NET_TCP_LOG_LEVEL=0
CONFIG_NET_TCP_BACKLOG_SIZE=1
# CONFIG_NET_TCP_AUTO_ACCEPT is not set
CONFIG_NET_TCP_TIME_WAIT_DELAY=250
CONFIG_NET_TCP_ACK_TIMEOUT=1000
CONFIG_NET_TCP_INIT_RETRANSMISSION_TIMEOUT=200
CONFIG_NET_TCP_RETRY_COUNT=9
CONFIG_NET_TCP_MAX_SEND_WINDOW_SIZE=0
CONFIG_NET_TCP_RECV_QUEUE_TIMEOUT=100
CONFIG_NET_TCP2=y
# CONFIG_NET_TCP1 is not set
# CONFIG_NET_TEST_PROTOCOL is not set
CONFIG_NET_UDP=y
CONFIG_NET_UDP_CHECKSUM=y
# CONFIG_NET_UDP_MISSING_CHECKSUM is not set
CONFIG_NET_UDP_LOG_LEVEL=0
CONFIG_NET_MAX_CONN=4
CONFIG_NET_MAX_CONTEXTS=6
CONFIG_NET_CONTEXT_NET_PKT_POOL=y
CONFIG_NET_CONTEXT_SYNC_RECV=y
CONFIG_NET_CONTEXT_CHECK=y
# CONFIG_NET_CONTEXT_PRIORITY is not set
# CONFIG_NET_CONTEXT_TIMESTAMP is not set
# CONFIG_NET_CONTEXT_TXTIME is not set
# CONFIG_NET_CONTEXT_RCVTIMEO is not set
# CONFIG_NET_TEST is not set
# CONFIG_NET_TRICKLE is not set
CONFIG_NET_PKT_RX_COUNT=16
CONFIG_NET_PKT_TX_COUNT=16
CONFIG_NET_BUF_RX_COUNT=80
CONFIG_NET_BUF_TX_COUNT=80
CONFIG_NET_BUF_FIXED_DATA_SIZE=y
# CONFIG_NET_BUF_VARIABLE_DATA_SIZE is not set
CONFIG_NET_BUF_DATA_SIZE=128
CONFIG_NET_DEFAULT_IF_FIRST=y
# CONFIG_NET_PKT_TIMESTAMP is not set
# CONFIG_NET_PKT_TXTIME is not set
# CONFIG_NET_PROMISCUOUS_MODE is not set

#
# Stack usage
#
CONFIG_NET_TX_STACK_SIZE=1200
CONFIG_NET_RX_STACK_SIZE=1500
# end of Stack usage

CONFIG_NET_MGMT=y
CONFIG_NET_MGMT_EVENT=y
CONFIG_NET_MGMT_EVENT_STACK_SIZE=768
CONFIG_NET_MGMT_EVENT_THREAD_PRIO=-1
CONFIG_NET_MGMT_EVENT_QUEUE_SIZE=2
CONFIG_NET_MGMT_EVENT_INFO=y
CONFIG_NET_MGMT_EVENT_LOG_LEVEL=0
# CONFIG_NET_DEBUG_MGMT_EVENT_STACK is not set
# CONFIG_NET_STATISTICS is not set
# CONFIG_NET_LOG is not set
CONFIG_NET_PKT_LOG_LEVEL=0
# CONFIG_NET_DEBUG_NET_PKT_ALLOC is not set
CONFIG_NET_DEBUG_NET_PKT_EXTERNALS=0
# CONFIG_NET_DEBUG_NET_PKT_NON_FRAGILE_ACCESS is not set
CONFIG_NET_CORE_LOG_LEVEL=0
CONFIG_NET_IF_LOG_LEVEL=0
CONFIG_NET_TC_LOG_LEVEL=0
CONFIG_NET_UTILS_LOG_LEVEL=0
CONFIG_NET_CONTEXT_LOG_LEVEL=0
CONFIG_NET_CONN_LOG_LEVEL=0
CONFIG_NET_ROUTE_LOG_LEVEL=0
# end of IP stack

#
# Network Protocols
#
# CONFIG_COAP is not set
# CONFIG_DNS_RESOLVER is not set
# CONFIG_DNS_SD is not set
# CONFIG_MQTT_LIB is not set
# CONFIG_TFTP_LIB is not set
CONFIG_HTTP_PARSER=y
CONFIG_HTTP_PARSER_URL=y
# CONFIG_HTTP_PARSER_STRICT is not set
CONFIG_HTTP_CLIENT=y
CONFIG_NET_HTTP_LOG_LEVEL=0
# CONFIG_WEBSOCKET_CLIENT is not set
# CONFIG_LWM2M is not set
# CONFIG_SOCKS is not set
# CONFIG_SNTP is not set
# end of Network Protocols

#
# Network Libraries
#
CONFIG_NET_CONFIG_AUTO_INIT=y
CONFIG_NET_CONFIG_INIT_PRIO=95
CONFIG_NET_CONFIG_INIT_TIMEOUT=30
# CONFIG_NET_CONFIG_NEED_IPV4 is not set
CONFIG_NET_CONFIG_LOG_LEVEL=0
# CONFIG_NET_CONFIG_SETTINGS is not set
CONFIG_NET_SOCKETS=y
CONFIG_NET_SOCKETS_POSIX_NAMES=y
CONFIG_NET_SOCKETS_POLL_MAX=4
CONFIG_NET_SOCKETS_CONNECT_TIMEOUT=3000
# CONFIG_NET_SOCKETS_SOCKOPT_TLS is not set
CONFIG_NET_SOCKETS_TLS_SET_MAX_FRAGMENT_LENGTH=y
CONFIG_NET_SOCKETS_OFFLOAD=y
CONFIG_NET_SOCKETS_OFFLOAD_TLS=y
# CONFIG_NET_SOCKETS_CAN is not set
# CONFIG_NET_SOCKETPAIR is not set
# CONFIG_NET_SOCKETS_NET_MGMT is not set
CONFIG_NET_SOCKETS_LOG_LEVEL=0
# CONFIG_TLS_CREDENTIALS is not set
# end of Network Libraries

#
# Network additional services
#
CONFIG_NET_CONNECTION_MANAGER=y
CONFIG_NET_CONNECTION_MANAGER_LOG_LEVEL=0
CONFIG_NET_CONNECTION_MANAGER_STACK_SIZE=512
CONFIG_NET_CONNECTION_MANAGER_PRIORITY=0
# end of Network additional services
# end of Networking

#
# Power Management
#
# CONFIG_SYS_POWER_MANAGEMENT is not set
# CONFIG_PM_STATE_LOCK is not set
# CONFIG_PM_DIRECT_FORCE_MODE is not set
# CONFIG_PM_DEBUG is not set
CONFIG_PM_POLICY_RESIDENCY=y
# CONFIG_PM_POLICY_DUMMY is not set
# CONFIG_PM_POLICY_APP is not set
CONFIG_PM_POLICY_RESIDENCY_DEFAULT=y
CONFIG_PM_MIN_RESIDENCY_DEEP_SLEEP_1=60000
# CONFIG_PM_LOG_LEVEL_OFF is not set
# CONFIG_PM_LOG_LEVEL_ERR is not set
# CONFIG_PM_LOG_LEVEL_WRN is not set
CONFIG_PM_LOG_LEVEL_INF=y
# CONFIG_PM_LOG_LEVEL_DBG is not set
CONFIG_PM_LOG_LEVEL=3
# CONFIG_DEVICE_POWER_MANAGEMENT is not set
# end of Power Management

# CONFIG_SHELL is not set
# CONFIG_STATS is not set
CONFIG_IMG_MANAGER=y
CONFIG_MCUBOOT_IMG_MANAGER=y
CONFIG_MCUBOOT_TRAILER_SWAP_TYPE=y
CONFIG_IMG_BLOCK_BUF_SIZE=512
CONFIG_IMG_ERASE_PROGRESSIVELY=y
# CONFIG_IMG_ENABLE_IMAGE_CHECK is not set
# CONFIG_IMG_MANAGER_LOG_LEVEL_OFF is not set
# CONFIG_IMG_MANAGER_LOG_LEVEL_ERR is not set
# CONFIG_IMG_MANAGER_LOG_LEVEL_WRN is not set
CONFIG_IMG_MANAGER_LOG_LEVEL_INF=y
# CONFIG_IMG_MANAGER_LOG_LEVEL_DBG is not set
CONFIG_IMG_MANAGER_LOG_LEVEL=3

#
# Random Number Generators
#
CONFIG_ENTROPY_DEVICE_RANDOM_GENERATOR=y
# CONFIG_XOROSHIRO_RANDOM_GENERATOR is not set
CONFIG_CSPRING_ENABLED=y
CONFIG_HARDWARE_DEVICE_CS_GENERATOR=y
# end of Random Number Generators

#
# Storage
#
CONFIG_FLASH_MAP=y
# CONFIG_FLASH_MAP_CUSTOM is not set
# CONFIG_FLASH_AREA_CHECK_INTEGRITY is not set
CONFIG_STREAM_FLASH=y
CONFIG_STREAM_FLASH_ERASE=y
# CONFIG_STREAM_FLASH_LOG_LEVEL_OFF is not set
# CONFIG_STREAM_FLASH_LOG_LEVEL_ERR is not set
# CONFIG_STREAM_FLASH_LOG_LEVEL_WRN is not set
CONFIG_STREAM_FLASH_LOG_LEVEL_INF=y
# CONFIG_STREAM_FLASH_LOG_LEVEL_DBG is not set
CONFIG_STREAM_FLASH_LOG_LEVEL=3
# end of Storage

# CONFIG_SETTINGS is not set

#
# Testing
#
# CONFIG_ZTEST is not set
# CONFIG_ZTEST_MOCKING is not set
# CONFIG_TEST is not set
# CONFIG_TEST_USERSPACE is not set
CONFIG_TEST_ARM_CORTEX_M=y
# end of Testing

# CONFIG_TIMING_FUNCTIONS is not set
# CONFIG_TRACING is not set
# end of Sub Systems and OS Services

CONFIG_TOOLCHAIN_ZEPHYR_0_15=y
CONFIG_TOOLCHAIN_ZEPHYR_SUPPORTS_THREAD_LOCAL_STORAGE=y

#
# Build and Link Features
#

#
# Linker Options
#
# CONFIG_LINKER_ORPHAN_SECTION_PLACE is not set
CONFIG_LINKER_ORPHAN_SECTION_WARN=y
# CONFIG_LINKER_ORPHAN_SECTION_ERROR is not set
# CONFIG_CODE_DATA_RELOCATION is not set
CONFIG_HAS_FLASH_LOAD_OFFSET=y
CONFIG_USE_DT_CODE_PARTITION=y
# CONFIG_HAVE_CUSTOM_LINKER_SCRIPT is not set
CONFIG_KERNEL_ENTRY="__start"
CONFIG_LINKER_SORT_BY_ALIGNMENT=y
# end of Linker Options

#
# Compiler Options
#
# CONFIG_CODING_GUIDELINE_CHECK is not set
# CONFIG_NATIVE_APPLICATION is not set
CONFIG_SIZE_OPTIMIZATIONS=y
# CONFIG_SPEED_OPTIMIZATIONS is not set
# CONFIG_DEBUG_OPTIMIZATIONS is not set
# CONFIG_NO_OPTIMIZATIONS is not set
CONFIG_COMPILER_OPT=""
# end of Compiler Options

# CONFIG_ASSERT_ON_ERRORS is not set
# CONFIG_NO_RUNTIME_CHECKS is not set
CONFIG_RUNTIME_ERROR_CHECKS=y

#
# Build Options
#
CONFIG_KERNEL_BIN_NAME="zephyr"
CONFIG_OUTPUT_STAT=y
CONFIG_OUTPUT_DISASSEMBLY=y
# CONFIG_OUTPUT_DISASSEMBLE_ALL is not set
CONFIG_OUTPUT_PRINT_MEMORY_USAGE=y
# CONFIG_CLEANUP_INTERMEDIATE_FILES is not set
# CONFIG_BUILD_NO_GAP_FILL is not set
CONFIG_BUILD_OUTPUT_BIN=y
# CONFIG_BUILD_OUTPUT_EXE is not set
# CONFIG_BUILD_OUTPUT_S19 is not set
# CONFIG_BUILD_OUTPUT_STRIPPED is not set
# CONFIG_APPLICATION_DEFINED_SYSCALL is not set
# CONFIG_MAKEFILE_EXPORTS is not set
# CONFIG_DEPRECATED_ZEPHYR_INT_TYPES is not set
# end of Build Options
# end of Build and Link Features

#
# Boot Options
#
# CONFIG_IS_BOOTLOADER is not set
CONFIG_BOOTLOADER_MCUBOOT=y
CONFIG_MCUBOOT_SIGNATURE_KEY_FILE=""
CONFIG_MCUBOOT_EXTRA_IMGTOOL_ARGS=""
# CONFIG_MCUBOOT_GENERATE_CONFIRMED_IMAGE is not set
CONFIG_REBOOT=y
# CONFIG_MISRA_SANE is not set
# end of Boot Options

#
# Compatibility
#
CONFIG_COMPAT_INCLUDES=y
# end of Compatibility

[ismail_embedded]

any feedback ?

[Susheel Nuguru]

Sorry Ismail for the late reply, I did not see any obvious configs that could cause this. But I need to have my colleagues look into this as well. I will try to get some feedback from my colleague tomorrow. Thanks for your patience so far.

[Susheel Nuguru]

Can you please give us the NCS version used? Also the modem firmware version.