Tool for flashing nrf52840 SoC while doing Firmware upgrade

Hi,

I'm using nrf52840SoC(flashed with open-thread rcp firmware) on a custom IMX-ULL-6 board. Is Jlink the only way to flash the firmware into the nrf52840 SoC

I'm asking this because after product deployment, if I want to provide a firmware upgrade to the devices, it won't be possible to use JLink, right

So,

1)Is there any other way to flash the firmware into the SoC?

2) Which upgrade method do you suggest for my use case with a firmware upgrade?

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  • Hi,

    For custom boards, you must also set the clock config in MCUboot. Child images do not inherit this configuration from the board file, so you must explicitly set it in the child image's configuration. You can set this in child_image/mcuboot.conf.

    Best regards,
    Marte

  • Hi,

    Can you specify the exact config name? 

    For more info,

    This is my mcuboot.conf

    CONFIG_SIZE_OPTIMIZATIONS=y
    CONFIG_SINGLE_APPLICATION_SLOT=y
    
    # Enable MCUboot Serial Recovery
    CONFIG_MCUBOOT_SERIAL=y
    CONFIG_UART_CONSOLE=n
    
    CONFIG_MCUBOOT_INDICATION_LED=y
    
    CONFIG_BOOT_SERIAL_UART=y
    CONFIG_BOOT_SERIAL_WAIT_FOR_DFU=y
    CONFIG_BOOT_SERIAL_WAIT_FOR_DFU_TIMEOUT=5000

    prj.conf is

    #
    # Copyright (c) 2020 Nordic Semiconductor
    #
    # SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
    #
    
    # Set OpenThread NCP architecture
    CONFIG_OPENTHREAD_COPROCESSOR=y
    CONFIG_OPENTHREAD_COPROCESSOR_RCP=y
    CONFIG_BOOTLOADER_MCUBOOT=y
    # Logging
    CONFIG_LOG=y
    CONFIG_OT_COPROCESSOR_LOG_LEVEL_ERR=y
    CONFIG_LOG_MAX_LEVEL=1
    CONFIG_OPENTHREAD_DEBUG=y
    CONFIG_OPENTHREAD_LOG_LEVEL_CRIT=y
    CONFIG_LOG_BACKEND_SPINEL=y
    CONFIG_LOG_BACKEND_RTT=n
    CONFIG_LOG_BACKEND_UART=n
    CONFIG_BOOT_BANNER=n
    
    # Increase logging thread stack size due to Spinel backend needs
    CONFIG_LOG_PROCESS_THREAD_STACK_SIZE=2048
    
    # Enable OpenThread features set
    CONFIG_OPENTHREAD_NORDIC_LIBRARY_MASTER=y
    
    CONFIG_NET_L2_OPENTHREAD=y
    
    # Generic networking options
    CONFIG_NETWORKING=y
    
    CONFIG_ASSERT=y
    CONFIG_ASSERT_NO_COND_INFO=y
    CONFIG_MBEDTLS_SHA1_C=n
    CONFIG_FPU=y

    My custom uart.overlay file

    /* Copyright (c) 2020 Nordic Semiconductor ASA
     *
     * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
     */
    
    &uart0 {
    	current-speed = <115200>;
    	status = "okay";
    	hw-flow-control;
    };
    
    / {
    	/*
    	* In some default configurations within the nRF Connect SDK,
    	* e.g. on nRF52840, the chosen zephyr,entropy node is &cryptocell.
    	* This devicetree overlay ensures that default is overridden wherever it
    	* is set, as this application uses the RNG node for entropy exclusively.
    	*/
    	chosen {
    		zephyr,entropy = &rng;
    		zephyr,console = &uart1;
    		zephyr,shell-uart = &uart1;
    		zephyr,uart-mcumgr = &uart0;
    		zephyr,bt-mon-uart = &uart0;
    		zephyr,bt-c2h-uart = &uart0;
    		zephyr,ot-uart = &uart0;
    	};
    
    	nrf_radio_coex: nrf_radio_coex_three_wire {
    		status = "okay";
    		compatible = "sdc-radio-coex-three-wire";
    		req-gpios = < &gpio0 0x3 (GPIO_ACTIVE_HIGH) >;
    		pri-dir-gpios = < &gpio0 0x4 (GPIO_ACTIVE_HIGH) >;
    		grant-gpios = < &gpio0 0x2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP) >;
    		type-delay-us = < 0x8 >;
    		radio-delay-us = < 0x5 >;
    	};
    };
    
    &pinctrl {
    	uart0_default: uart0_default {
    		group1 {
    			psels = <NRF_PSEL(UART_TX, 0, 29)>,
    					<NRF_PSEL(UART_RTS, 1, 13)>;
    		};
    		group2 {
    			psels = <NRF_PSEL(UART_RX, 0, 31)>,
    					<NRF_PSEL(UART_CTS, 1, 15)>;
    			bias-pull-up;
    		};
    	};
    
    	uart0_sleep: uart0_sleep {
    		group1 {
    			psels = <NRF_PSEL(UART_TX, 0, 29)>,
    				<NRF_PSEL(UART_RTS, 1, 13)>,
    				<NRF_PSEL(UART_RX, 0, 31)>,
    				<NRF_PSEL(UART_CTS, 1, 15)>;
    			low-power-enable;
    		};
    	};
    
    	uart1_me: uart1_me {
    		group1 {
    			psels = <NRF_PSEL(UART_TX, 0, 9)>;
    		};
    		group2 {
    			psels = <NRF_PSEL(UART_RX, 0, 10)>;
    			bias-pull-up;
    		};
    	};
    
    	uart1_sleep_me: uart1_sleep_me {
    		group1 {
    			psels = <NRF_PSEL(UART_TX, 0, 9)>,
    				<NRF_PSEL(UART_RX, 0, 10)>;
    			low-power-enable;
    		};
    	};
    };
    
    &uart1 {
    	status = "okay";
    	current-speed = < 0x1c200 >;
    	pinctrl-0 = < &uart1_me >;
    	pinctrl-1 = < &uart1_sleep_me >;
    	pinctrl-names = "default", "sleep";
    };

    Does any other thing need to be modified in the above configs?

    Thanks.

  • Hi,

    The config depends on your clock source, and it should be the same as what you have defined for the board itself in the board files.

    Here are two possibilities.
    If you have, for example, a 32kHz RC clock source, then you should set the following:

    CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
    CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n
    CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION=y

    For a 32kHz crystal oscillator, you need to set this instead in the child image:

    CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y

    Best regards,
    Marte

  • Hi,

    I've also added this and tested. But still it's not working. Are you seeing anything wrong in my above config files or do you have any other suggestions.

    Thanks.

  • Hi,

    Are you able to run other programs successfully on your custom board?

    Best regards,
    Marte

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