MCUBoot without Partition Manager

[BenKrug]

Hi, I want to implement DFU on an nRF52832 with a mx25r1635f external flash, originally I implement the partitions and everything using the devicetree since I find it a lot more comfortable to use. I followed this proccess: https://devzone.nordicsemi.com/guides/nrf-connect-sdk-guides/b/software/posts/ncs-dfu , but the CONFIG_BOOTLOADER_MCUBOOT option enables the partition manager by default, is there a way to use it with the devicetree method for partitions? I saw that most applications on Zephyr do actually use the devicetree instead of the partition manager, so I expect it to be possible, but couldn't find a way to do it.

[Amanda Hsieh]

Check the CONFIG_PM_PARTITION_SIZE_LITTLEFS value. 

-Amanda H.

[BenKrug]

I'm getting this error now when I set CONFIG_PM_PARTITION_SIZE_LITTLEFS to any value bigger than 0xf000:

do you know what could it be?

[BenKrug]

even when the value is 0x7000, it still gives this error: 

[Amanda Hsieh]

Hi, 

Could you provide the memory layout for the partition, partitions.yml under build folder, overlay, and config files? If you are using pm_static.yml, please also share it. 

-Amanda H.

[BenKrug]

The memory report I can't generate, when I try to generate it, it gives me an error.
partitions.yml:

app:
  address: 0xc200
  end_address: 0x80000
  region: flash_primary
  size: 0x73e00
external_flash:
  address: 0x83000
  end_address: 0x200000
  region: external_flash
  size: 0x17d000
littlefs_storage:
  address: 0x74000
  device: DT_CHOSEN(nordic_pm_ext_flash)
  end_address: 0x83000
  placement:
    before:
    - tfm_storage
    - end
  region: external_flash
  size: 0xf000
mcuboot:
  address: 0x0
  end_address: 0xc000
  placement:
    before:
    - mcuboot_primary
  region: flash_primary
  size: 0xc000
mcuboot_pad:
  address: 0xc000
  end_address: 0xc200
  placement:
    before:
    - mcuboot_primary_app
  region: flash_primary
  size: 0x200
mcuboot_primary:
  address: 0xc000
  end_address: 0x80000
  orig_span: &id001
  - app
  - mcuboot_pad
  region: flash_primary
  size: 0x74000
  span: *id001
mcuboot_primary_app:
  address: 0xc200
  end_address: 0x80000
  orig_span: &id002
  - app
  region: flash_primary
  size: 0x73e00
  span: *id002
mcuboot_secondary:
  address: 0x0
  device: DT_CHOSEN(nordic_pm_ext_flash)
  end_address: 0x74000
  placement:
    align:
      start: 0x4
  region: external_flash
  share_size:
  - mcuboot_primary
  size: 0x74000
sram_primary:
  address: 0x20000000
  end_address: 0x20010000
  region: sram_primary
  size: 0x10000

overlay file:

/*
 * Copyright (c) 2019 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

&pinctrl {
    spi0_default: spi0_default {
        group1 {
            psels = <NRF_PSEL(SPIM_SCK, 0, 6)>,
				<NRF_PSEL(SPIM_MOSI, 0, 5)>,
				<NRF_PSEL(SPIM_MISO, 0, 4)>;
        };
    };

	spi0_sleep: spi0_sleep {
        group1 {
            psels = <NRF_PSEL(SPIM_SCK, 0, 6)>,
				<NRF_PSEL(SPIM_MOSI, 0, 5)>,
				<NRF_PSEL(SPIM_MISO, 0, 4)>;
				low-power-enable;
        };
    };

    spi1_default: spi1_default {
        group1 {
            psels = <NRF_PSEL(SPIM_SCK, 0, 14)>,
				<NRF_PSEL(SPIM_MOSI, 0, 13)>,
				<NRF_PSEL(SPIM_MISO, 0, 16)>;
        };
    };
	
	spi1_sleep: spi1_sleep {
        group1 {
            psels = <NRF_PSEL(SPIM_SCK, 0, 14)>,
				<NRF_PSEL(SPIM_MOSI, 0, 13)>,
				<NRF_PSEL(SPIM_MISO, 0, 16)>;
				low-power-enable;
        };
    };

	uart1_default: uart1_default {
		group1 {
			psels = <NRF_PSEL(UART_RX, 0, 18)>;
			bias-pull-up;
		};
		group2 {
			psels = <NRF_PSEL(UART_TX, 0, 2)>;
			// max. 5mA drive strength: 
			nordic,drive-mode = <NRF_DRIVE_H0D1>;
		};
	};
};

&adc {
	#address-cells = <1>;
	#size-cells = <0>;

	channel@7 {
		reg = <7>;
		zephyr,gain = "ADC_GAIN_1_6";
		zephyr,reference = "ADC_REF_INTERNAL";
		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
		zephyr,input-positive = <NRF_SAADC_AIN7>; /* P0.03 */
		zephyr,resolution = <12>;
	};
};

&spi0 {
	compatible = "nordic,nrf-spi";
	status = "okay";
	cs-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
	lsm6dsl@0 {
		compatible = "st,lsm6dsl";
		reg = <0>;
		spi-max-frequency = <4300000>;
	};
};

&spi1 {
	compatible = "nordic,nrf-spi";
	status = "okay";
	cs-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
};



/ {
	
	fstab {
		compatible = "zephyr,fstab";
		lfs1: lfs1 {
			compatible = "zephyr,fstab,littlefs";
			mount-point = "/lfs1";
			partition = <&lfs1_part>;
			automount;
			read-size = <16>;
			prog-size = <16>;
			cache-size = <128>;
			lookahead-size = <32>;
			block-cycles = <32>;
		};
	};
	
	zephyr,user {
		io-channels = <&adc 7>;
	};
	chosen {
		nordic,pm-ext-flash = &mx25r16;
	};
};


&mx25r16 {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;
		lfs1_part: partition@0 {
			label = "lfs1_storage";
			reg = <0x00000000 0x1000000>;
		};
	};
};

config file:

CONFIG_JSON_LIBRARY=y
CONFIG_CBPRINTF_FP_SUPPORT=y
CONFIG_DEBUG=y
CONFIG_CPLUSPLUS=y
CONFIG_LIB_CPLUSPLUS=y
CONFIG_NEWLIB_LIBC=y
CONFIG_NEWLIB_LIBC_FLOAT_PRINTF=y
CONFIG_SIZE_OPTIMIZATIONS=y

CONFIG_CONSOLE=y
CONFIG_USE_SEGGER_RTT=y
CONFIG_RTT_CONSOLE=y

CONFIG_THREAD_CUSTOM_DATA=n

CONFIG_FPU=y
CONFIG_FP16=n
CONFIG_EDGE_IMPULSE=y
CONFIG_EDGE_IMPULSE_URI="http://studio.edgeimpulse.com/v1/api/160376/deployment/download?type=zip"
CONFIG_EI_WRAPPER=y

CONFIG_LOG=y
CONFIG_LOG_DEFAULT_LEVEL=1
#CONFIG_LOG_MODE_IMMEDIATE=y

CONFIG_ADC=y
CONFIG_SENSOR=y
CONFIG_SPI=y

CONFIG_SPI_NOR=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_FLASH_PAGE_LAYOUT=y
CONFIG_MPU_ALLOW_FLASH_WRITE=y

CONFIG_FILE_SYSTEM=y
CONFIG_FILE_SYSTEM_LITTLEFS=y
CONFIG_PM_EXTERNAL_FLASH_MCUBOOT_SECONDARY=y

CONFIG_PM_PARTITION_SIZE_LITTLEFS=0xf000
#CONFIG_PM_PARTITION_REGION_LITTLEFS_EXTERNAL=y
#CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y
#CONFIG_FS_LITTLEFS_CACHE_SIZE=128

CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y
CONFIG_BT_HCI_TX_STACK_SIZE=640
CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2000
CONFIG_MPSL_WORK_STACK_SIZE=640
CONFIG_MAIN_STACK_SIZE=3000
CONFIG_IDLE_STACK_SIZE=128
CONFIG_ISR_STACK_SIZE=1024

CONFIG_BT=y
CONFIG_BT_HCI=y
CONFIG_BT_BONDABLE=y
CONFIG_BT_SMP=y
CONFIG_BT_SIGNING=y
CONFIG_BT_PERIPHERAL=y
CONFIG_BT_PRIVACY=n
CONFIG_BT_ATT_PREPARE_COUNT=10
CONFIG_BT_DEVICE_APPEARANCE=833
CONFIG_BT_DEVICE_NAME_DYNAMIC=y
CONFIG_BT_DEVICE_NAME_MAX=65
CONFIG_BT_L2CAP_TX_MTU=100
CONFIG_BT_RX_STACK_SIZE=3000
CONFIG_BT_DEBUG_NONE=y
CONFIG_BT_ASSERT=n
CONFIG_BT_DATA_LEN_UPDATE=n
CONFIG_BT_PHY_UPDATE=n
CONFIG_BT_GATT_CACHING=n
CONFIG_BT_GATT_SERVICE_CHANGED=y
CONFIG_BT_GAP_PERIPHERAL_PREF_PARAMS=n
CONFIG_BT_HCI_VS_EXT=n
CONFIG_TIMESLICING=n

# Disable Bluetooth controller features not needed
CONFIG_BT_CTLR_PRIVACY=n

# Reduce Bluetooth buffers
CONFIG_BT_BUF_EVT_DISCARDABLE_COUNT=1
CONFIG_BT_BUF_EVT_RX_COUNT=2

CONFIG_BT_L2CAP_TX_BUF_COUNT=2
CONFIG_BT_BUF_ACL_TX_SIZE=256

#habilita update bia BLE
# Enable mcumgr.
CONFIG_MCUMGR=y

# Enable most core commands.
CONFIG_MCUMGR_CMD_IMG_MGMT=y
CONFIG_MCUMGR_CMD_OS_MGMT=y
CONFIG_MCUMGR_SMP_BT=y
CONFIG_MCUMGR_SMP_BT_AUTHEN=n


# Ensure an MCUboot-compatible binary is generated.
CONFIG_BOOTLOADER_MCUBOOT=y
CONFIG_IMG_MANAGER=y
CONFIG_DFU_TARGET=y
CONFIG_DFU_TARGET_MCUBOOT=y
CONFIG_IMG_ERASE_PROGRESSIVELY=y

I have no pm_static.yml file.