Enabling pins P0.0, P0.1, P0.2, P0.3, and P0.19 as GPIO [NRF5340]

Hey y'all,

I'm having trouble enabling these pins as GPIO for our custom nrf5340 board, and from reading around, it's not clear to me as a beginner how to properly configure these pins.

Pins  P0.0 and P0.1 are usually used to operate an oscillator, but our board doesn't need it and instead these pins should operate as GPIO pins. My understanding is that to enable these pins, I need to operate the chip with the internal oscillator which I can do with the following lines in my proj.conf.

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n

Pins P0.2 and P0.3 are typically used for an NFC antenna, but again, our board doesn't need this functionality and these pins should be configured to be used as GPIO. My understanding is that all I need to do is add the following line to my proj.conf. 

I've read that these pins can only be used in a "secure domain", but I've tried creating different projects types (nrf5340dk_nrf5340_cpuapp_ns and nrf5340dk_nrf5340_cpuapp) and running them to no success. There is probably a misunderstanding here on my part. I get the same results as the following link (https://devzone.nordicsemi.com/f/nordic-q-a/94197/config_nfct_pins_as_gpios-y-doesn-t-work). Please direct me to resources to deepen my understanding of a secure domain so I can fix the issue.

CONFIG_NFCT_PINS_AS_GPIOS=y

Pin P.019 is the most confusing to me. On the dev kit, this pin along with pins P0.20, P0.21, P0.22 are used to make a virtual com port. Other than that though, from the manual, it seems like a normal GPIO pin with no other functionalities. It is unclear to me why this pin is not working. I've done my best to verify that the hardware and connections for this pin on the custom board are working. I'm also unable to toggle this pin on the dev board, despite making the needed physical changes to do so. Is there a setting to enable this particular pin?

If it helps, I'm using VSCode on Ubuntu.

Thanks for the help. I've included the full proj.conf and the overlay file below.

CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n

# I2C
CONFIG_I2C=y
CONFIG_NRFX_TWIM1=y

CONFIG_PRINTK=y


# Rebooot
CONFIG_REBOOT=n
CONFIG_RESET_ON_FATAL_ERROR=n

CONFIG_NFCT_PINS_AS_GPIOS=y

// To get started, press Ctrl+Space to bring up the completion menu and view the available nodes.

// You can also use the buttons in the sidebar to perform actions on nodes.
// Actions currently available include:

// * Enabling / disabling the node
// * Adding the bus to a bus
// * Removing the node
// * Connecting ADC channels

// For more help, browse the DeviceTree documentation at https://docs.zephyrproject.org/latest/guides/dts/index.html
// You can also visit the nRF DeviceTree extension documentation at https://nrfconnect.github.io/vscode-nrf-connect/devicetree/nrfdevicetree.html
/ {
	userpins {
		compatible = "gpio-keys";
		ex1: ex_1 {
			gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 1";
		};
		ex2: ex_2 {
			gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 2";
		};
		ex3: ex_3 {
			gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 3";
		};
		ex4: ex_4 {
			gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 4";
		};
		ex5: ex_5 {
			gpios = <&gpio0 24 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 5";
		};
		ex6: ex_6 {
			gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 6";
		};
		ex7: ex_7 {
			gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 7";
		};
		ex8: ex_8 {
			gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 8";
		};
		ex9: ex_9 {
			gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 9";
		};
		ex10: ex_10 {
			gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 10";
		};
		ex11: ex_11 {
			gpios = <&gpio0 30 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 11";
		};
		ex12: ex_12 {
			gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "External pin 12";
		};
		enl: en_l {
			gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Enable LED Mux";
		};
		mux0: mux_0 {
			gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "LED Mux select 0";
		};
		mux1: mux_1 {
			gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "LED Mux select 1";
		};
		mux2: mux_2 {
			gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "LED Mux select 2";
		};
		smux0: smux_0 {
			gpios = <&gpio1 8 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Stepper Mux select 0";
		};
		smux1: smux_1 {
			gpios = <&gpio1 9 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Stepper Mux select 1";
		};
		smux2: smux_2 {
			gpios = <&gpio1 10 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Stepper Mux select 2";
		};
		smux3: smux_3 {
			gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Stepper Mux select 3";
		};
		ens: en_s {
			gpios = <&gpio1 12 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Enable stepper motors";
		};
		clks: clk_s {
			gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Clock for stepper motors";
		};
		steps: step_s {
			gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Step pin for stepper motors";
		};
		dirs: dir_s {
			gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Dir pin for stepper motors";
		};
		mmux0: mmux_0 {
			gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Misc mux select 0";
		};
		mmux1: mmux_1 {
			gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Misc mux select 1";
		};
		mmux2: mmux_2 {
			gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Misc mux select 2";
		};
		clkm: clk_m {
			gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Clock for miscellaneous";
		};
		miscm: misc_m {
			gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Misc input";
		};
		lmux0: lmux_0 {
			gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Limit mux select 0";
		};
		lmux1: lmux_1 {
			gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Limit mux select 1";
		};
		lmux2: lmux_2 {
			gpios = <&gpio0 18 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Limit mux select 2";
		};
		lmux3: lmux_3 {
			gpios = <&gpio0 19 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Limit mux select 3";
		};
		lmt: lmt {
			gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Limit pin";
		};
		serv0: serv_0 {
			gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Servo 0 pin";
		};
		serv1: serv_1 {
			gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Servo 1 pin";
		};
		serv2: serv_2 {
			gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Servo 2 pin";
		};
		serv3: serv_3 {
			gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_VOLTAGE_3P3)>;
			label = "Servo 3 pin";
		};
	};
};

&i2c1 {
	status = "okay";
	compatible = "nordic,nrf-twim";
	label = "I2C_1";
	pinctrl-0 = <&i2c1_default>;
	pinctrl-1 = <&i2c1_sleep>;
	pinctrl-names = "default", "sleep";
	clock-frequency = <100000>; 

	bh1749: bh1749@38 {
		compatible = "rohm,bh1749";
		label = "BH1749";
		reg = <0x38>;
		int-gpios = <&gpio0 27 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
	};

	tca9548: tca9548a@70 {
		compatible = "ti,tca9548a";
		label = "TCA9548";
		reg = <0x70>;
	};
};

&pinctrl {
	i2c1_default: i2c1_default{
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 0, 35)>,
				<NRF_PSEL(TWIM_SCL, 0, 34)>;
		};
	};

	i2c1_sleep: i2c1_sleep{
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 0, 35)>,
				<NRF_PSEL(TWIM_SCL, 0, 34)>;
			low-power-enable;
		};
	};
};

Parents Reply Children
  • Thanks for the advice and links. I did my best to read them and follow them closely. I had already completed the Nordic Dev Academy prior to posting. It was a great help.

    Unfortunately I've been unable to create my own board files. I went through the dts files of the semi-working project (the one where some of the pins don't work) to create the files. I've included the relevant files below. I'm getting the following error, which I assume is happening because I didn't make my board files properly. Please let me know where my understanding might be breaking down.

    ...

    [150/162] Building C object zephyr/kernel/CMakeFiles/kernel.dir/timeout.c.obj
    [151/162] Linking C static library zephyr/kernel/libkernel.a
    [152/162] Linking C executable zephyr/zephyr_pre0.elf
    FAILED: zephyr/zephyr_pre0.elf zephyr/zephyr_pre0.map
    : && ccache /home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk/arm-zephyr-eabi/bin/arm-zephyr-eabi-gcc  -gdwarf-4 zephyr/CMakeFiles/zephyr_pre0.dir/misc/empty_file.c.obj -o zephyr/zephyr_pre0.elf  -fuse-ld=bfd  -Wl,-T  zephyr/linker_zephyr_pre0.cmd  -Wl,-Map=/home/james/org/work/nrf/ncs_projects/blinky/build/zephyr/zephyr_pre0.map  -Wl,--whole-archive  app/libapp.a  zephyr/libzephyr.a  zephyr/arch/common/libarch__common.a  zephyr/arch/arch/arm/core/aarch32/libarch__arm__core__aarch32.a  zephyr/arch/arch/arm/core/aarch32/cortex_m/libarch__arm__core__aarch32__cortex_m.a  zephyr/arch/arch/arm/core/aarch32/cortex_m/cmse/libarch__arm__core__aarch32__cortex_m__cmse.a  zephyr/arch/arch/arm/core/aarch32/mpu/libarch__arm__core__aarch32__mpu.a  zephyr/lib/libc/minimal/liblib__libc__minimal.a  zephyr/soc/arm/common/cortex_m/libsoc__arm__common__cortex_m.a  zephyr/drivers/clock_control/libdrivers__clock_control.a  zephyr/drivers/i2c/libdrivers__i2c.a  zephyr/drivers/timer/libdrivers__timer.a  modules/nrf/drivers/hw_cc310/lib..__nrf__drivers__hw_cc310.a  modules/hal_nordic/nrfx/libmodules__hal_nordic__nrfx.a  -Wl,--no-whole-archive  zephyr/kernel/libkernel.a  zephyr/CMakeFiles/offsets.dir/./arch/arm/core/offsets/offsets.c.obj  -L"/home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/thumb/v8-m.main/nofp"  -L/home/james/org/work/nrf/ncs_projects/blinky/build/zephyr  -lgcc  zephyr/arch/common/libisr_tables.a  -mcpu=cortex-m33  -mthumb  -mabi=aapcs  -Wl,--gc-sections  -Wl,--build-id=none  -Wl,--sort-common=descending  -Wl,--sort-section=alignment  -Wl,-u,_OffsetAbsSyms  -Wl,-u,_ConfigAbsSyms  -nostdlib  -static  -Wl,-X  -Wl,-N  -Wl,--orphan-handling=warn  -Wl,-no-pie  /home/james/ncs/v2.4.0/nrfxlib/crypto/nrf_cc312_platform/lib/cortex-m33/soft-float/no-interrupts/libnrf_cc312_platform_0.9.17.a && cd /home/james/org/work/nrf/ncs_projects/blinky/build/zephyr && /home/james/ncs/toolchains/1f9b40e71a/usr/local/bin/cmake -E echo
    /home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: app/libapp.a(main.c.obj): in function `main':
    /home/james/org/work/nrf/ncs_projects/blinky/src/main.c:82: undefined reference to `__device_dts_ord_92'
    /home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: app/libapp.a(main.c.obj):(.rodata.lmt_0+0x0): undefined reference to `__device_dts_ord_92'
    /home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: app/libapp.a(main.c.obj):(.rodata.lmux_3+0x0): undefined reference to `__device_dts_ord_92'
    /home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: app/libapp.a(main.c.obj):(.rodata.lmux_2+0x0): undefined reference to `__device_dts_ord_92'
    /home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: app/libapp.a(main.c.obj):(.rodata.lmux_1+0x0): undefined reference to `__device_dts_ord_92'
    /home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: app/libapp.a(main.c.obj):(.rodata.lmux_0+0x0): more undefined references to `__device_dts_ord_92' follow
    /home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: zephyr/drivers/i2c/libdrivers__i2c.a(i2c_nrfx_twim.c.obj): in function `pinctrl_apply_state':
    /home/james/ncs/v2.4.0/zephyr/include/zephyr/drivers/pinctrl.h:348: undefined reference to `pinctrl_lookup_state'
    /home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: zephyr/drivers/i2c/libdrivers__i2c.a(i2c_nrfx_twim.c.obj): in function `pinctrl_apply_state_direct':
    /home/james/ncs/v2.4.0/zephyr/include/zephyr/drivers/pinctrl.h:329: undefined reference to `pinctrl_configure_pins'
    collect2: error: ld returned 1 exit status
    ninja: build stopped: subcommand failed.
    FATAL ERROR: command exited with status 1: /home/james/ncs/toolchains/1f9b40e71a/usr/local/bin/cmake --build /home/james/org/work/nrf/ncs_projects/blinky/build

    main.c

    /*
     * Copyright (c) 2016 Intel Corporation
     *
     * SPDX-License-Identifier: Apache-2.0
     */
    
    #include <zephyr/kernel.h>
    #include <zephyr/drivers/gpio.h>
    #include <zephyr/zephyr.h>
    #include <zephyr/drivers/i2c.h>
    #include <zephyr/drivers/pinctrl.h>
    #include <zephyr/device.h>
    
    /* 1000 msec = 1 sec */
    #define SLEEP_TIME_MS   1000
    
    /*
     * A build error on this line means your board is unsupported.
     * See the sample documentation for information on how to fix this.
     */
    #define LMUX0_NODE DT_NODELABEL(lmux0)
    #define LMUX1_NODE DT_NODELABEL(lmux1)
    #define LMUX2_NODE DT_NODELABEL(lmux2)
    #define LMUX3_NODE DT_NODELABEL(lmux3)
    #define LMT_NODE DT_NODELABEL(lmt)
    
    static const struct gpio_dt_spec lmux_0 = GPIO_DT_SPEC_GET_OR(LMUX0_NODE, gpios, {0});
    static const struct gpio_dt_spec lmux_1 = GPIO_DT_SPEC_GET_OR(LMUX1_NODE, gpios, {0});
    static const struct gpio_dt_spec lmux_2 = GPIO_DT_SPEC_GET_OR(LMUX2_NODE, gpios, {0});
    static const struct gpio_dt_spec lmux_3 = GPIO_DT_SPEC_GET_OR(LMUX3_NODE, gpios, {0});
    static const struct gpio_dt_spec lmt_0 = GPIO_DT_SPEC_GET_OR(LMT_NODE, gpios, {0});
    
    int main(void)
    {
    	int ret;
    
    	if (!device_is_ready(lmux_0.port)) {
    		return -1;
    	}
    	if (!device_is_ready(lmux_1.port)) {
    		return -1;
    	}
    	if (!device_is_ready(lmux_2.port)) {
    		return -1;
    	}
    	if (!device_is_ready(lmux_3.port)) {
    		return -1;
    	}
    	if (!device_is_ready(lmt_0.port)) {
    		return -1;
    	}
    
    	ret = gpio_pin_configure_dt(&lmux_0, GPIO_OUTPUT_LOW);
    	if (ret < 0) {
    		return ret;
    	}
    	ret = gpio_pin_configure_dt(&lmux_1, GPIO_OUTPUT_LOW);
    	if (ret < 0) {
    		return ret;
    	}
    	ret = gpio_pin_configure_dt(&lmux_2, GPIO_OUTPUT_LOW);
    	if (ret < 0) {
    		return ret;
    	}
    	ret = gpio_pin_configure_dt(&lmux_3, GPIO_OUTPUT_LOW);
    	if (ret < 0) {
    		return ret;
    	}
    	ret = gpio_pin_configure_dt(&lmt_0, GPIO_INPUT);
    	if (ret < 0) {
    		return ret;
    	}
    
    	while (1) {
    		ret = gpio_pin_toggle_dt(&lmux_3);
    		if (ret < 0) {
    			return 0;
    		}
    		k_msleep(SLEEP_TIME_MS);
    	}
    	return 0;
    }
    

    nrf5340_tricca_board.dts

    /dts-v1/;
    
    #include <nordic/nrf5340_cpuapp_qkaa.dtsi>
    #include <nordic/nrf5340_tricca_board.dtsi>
    / {
    	model = "nrf5340 Tricca Board";
    	compatible = "tricca-technologies-inc-,nrf5340-tricca-board";
    
    	chosen {
    		zephyr,sram = &sram0;
    		zephyr,flash = &flash0;
    		zephyr,code-partition = &slot0_partition;
    		zephyr,console = &uart0;
    		zephyr,shell-uart = &uart0;
    		zephyr,uart-mcumgr = &uart0;
    		zephyr,bt-mon-uart = &uart0;
    		zephyr,bt-c2h-uart = &uart0;
    		zephyr,bt-hci-rpmsg-ipc = &ipc0;
    		nordic,802154-spinel-ipc = &ipc0;
    		zephyr,ieee802154 = &ieee802154;
    		/* shared memory reserved for the inter-processor communication */
    		zephyr,ipc_shm = &sram0_shared;
    	};
    
    	reserved-memory {
    		#address-cells = <1>;
    		#size-cells = <1>;
    		ranges;
    
    		sram0_image: image@20000000 {
    			/* Zephyr image(s) memory */
    		};
    
    		sram0_s: image_s@20000000 {
    			/* Secure image memory */
    		};
    
    		sram0_ns: image_ns@20040000 {
    			/* Non-Secure image memory */
    		};
    
    		sram0_shared: memory@20070000 {
    			/* SRAM allocated to shared memory */
    			reg = <0x20070000 0x10000>;
    		};
    	};
    };
    
    &gpio0 {
    	status = "okay";
    };
    
    &gpio1 {
    	status = "okay";
    };
    
    &i2c1 {
    	compatible = "nordic,nrf-twim";
    	status = "okay";
    	pinctrl-0 = <&i2c1_default>;
    	pinctrl-1 = <&i2c1_sleep>;
    	pinctrl-names = "default", "sleep";
    };
    
    &flash0 {
    
    	partitions {
    		compatible = "fixed-partitions";
    		#address-cells = <1>;
    		#size-cells = <1>;
    
    		boot_partition: partition@0 {
    			label = "mcuboot";
    			reg = <0x00000000 0x00010000>;
    		};
    		slot0_partition: partition@10000 {
    			label = "image-0";
    		};
    		slot0_ns_partition: partition@50000 {
    			label = "image-0-nonsecure";
    		};
    		slot1_partition: partition@80000 {
    			label = "image-1";
    		};
    		slot1_ns_partition: partition@c0000 {
    			label = "image-1-nonsecure";
    		};
    		/* 0xf0000 to 0xf7fff reserved for TF-M partitions */
    		storage_partition: partition@f8000 {
    			label = "storage";
    			reg = <0x000f8000 0x00008000>;
    		};
    	};
    };
    
    &ieee802154 {
    	status = "okay";
    };
    
    &slot0_partition {
    	reg = <0x00010000 0x40000>;
    };
    
    &slot0_ns_partition {
    	reg = <0x00050000 0x30000>;
    };
    
    &slot1_partition {
    	reg = <0x00080000 0x40000>;
    };
    
    &slot1_ns_partition {
    	reg = <0x000c0000 0x30000>;
    };
    
    &sram0_image {
    	reg = <0x20000000 DT_SIZE_K(448)>;
    };
    
    &sram0_s {
    	reg = <0x20000000 0x40000>;
    };
    
    &sram0_ns {
    	reg = <0x20040000 0x30000>;
    };
    

    nrf5340_tricca_board.overlay

    // To get started, press Ctrl+Space to bring up the completion menu and view the available nodes.
    
    // You can also use the buttons in the sidebar to perform actions on nodes.
    // Actions currently available include:
    
    // * Enabling / disabling the node
    // * Adding the bus to a bus
    // * Removing the node
    // * Connecting ADC channels
    
    // For more help, browse the DeviceTree documentation at https://docs.zephyrproject.org/latest/guides/dts/index.html
    // You can also visit the nRF DeviceTree extension documentation at https://nrfconnect.github.io/vscode-nrf-connect/devicetree/nrfdevicetree.html
    / {
    	userpins {
    		compatible = "gpio-keys";
    		ex1: ex_1 {
    			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
    			label = "External pin 1";
    		};
    		ex2: ex_2 {
    			gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
    			label = "External pin 2";
    		};
    		ex3: ex_3 {
    			gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
    			label = "External pin 3";
    		};
    		ex4: ex_4 {
    			gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
    			label = "External pin 4";
    		};
    		ex5: ex_5 {
    			gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
    			label = "External pin 5";
    		};
    		ex6: ex_6 {
    			gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
    			label = "External pin 6";
    		};
    		ex7: ex_7 {
    			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
    			label = "External pin 7";
    		};
    		ex8: ex_8 {
    			gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
    			label = "External pin 8";
    		};
    		ex9: ex_9 {
    			gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
    			label = "External pin 9";
    		};
    		ex10: ex_10 {
    			gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
    			label = "External pin 10";
    		};
    		ex11: ex_11 {
    			gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
    			label = "External pin 11";
    		};
    		ex12: ex_12 {
    			gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
    			label = "External pin 12";
    		};
    		enl: en_l {
    			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
    			label = "Enable LED Mux";
    		};
    		mux0: mux_0 {
    			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
    			label = "LED Mux select 0";
    		};
    		mux1: mux_1 {
    			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
    			label = "LED Mux select 1";
    		};
    		mux2: mux_2 {
    			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
    			label = "LED Mux select 2";
    		};
    		smux0: smux_0 {
    			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
    			label = "Stepper Mux select 0";
    		};
    		smux1: smux_1 {
    			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
    			label = "Stepper Mux select 1";
    		};
    		smux2: smux_2 {
    			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
    			label = "Stepper Mux select 2";
    		};
    		smux3: smux_3 {
    			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
    			label = "Stepper Mux select 3";
    		};
    		ens: en_s {
    			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
    			label = "Enable stepper motors";
    		};
    		clks: clk_s {
    			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
    			label = "Clock for stepper motors";
    		};
    		steps: step_s {
    			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
    			label = "Step pin for stepper motors";
    		};
    		dirs: dir_s {
    			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
    			label = "Dir pin for stepper motors";
    		};
    		mmux0: mmux_0 {
    			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
    			label = "Misc mux select 0";
    		};
    		mmux1: mmux_1 {
    			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
    			label = "Misc mux select 1";
    		};
    		mmux2: mmux_2 {
    			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
    			label = "Misc mux select 2";
    		};
    		clkm: clk_m {
    			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
    			label = "Clock for miscellaneous";
    		};
    		miscm: misc_m {
    			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
    			label = "Misc input";
    		};
    		lmux0: lmux_0 {
    			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
    			label = "Limit mux select 0";
    		};
    		lmux1: lmux_1 {
    			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
    			label = "Limit mux select 1";
    		};
    		lmux2: lmux_2 {
    			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
    			label = "Limit mux select 2";
    		};
    		lmux3: lmux_3 {
    			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
    			label = "Limit mux select 3";
    		};
    		lmt: lmt {
    			gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
    			label = "Limit pin";
    		};
    		serv0: serv_0 {
    			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
    			label = "Servo 0 pin";
    		};
    		serv1: serv_1 {
    			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
    			label = "Servo 1 pin";
    		};
    		serv2: serv_2 {
    			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
    			label = "Servo 2 pin";
    		};
    		serv3: serv_3 {
    			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
    			label = "Servo 3 pin";
    		};
    	};
    };
    
    &i2c1 {
    	status = "okay";
    	compatible = "nordic,nrf-twim";
    	label = "I2C_1";
    	pinctrl-0 = <&i2c1_default>;
    	pinctrl-1 = <&i2c1_sleep>;
    	pinctrl-names = "default", "sleep";
    	clock-frequency = <100000>;
    
    	bh1749: bh1749@38 {
    		compatible = "rohm,bh1749";
    		label = "BH1749";
    		reg = <0x38>;
    		int-gpios = <&gpio0 27 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
    	};
    
    	tca9548: tca9548a@70 {
    		compatible = "ti,tca9548a";
    		label = "TCA9548";
    		reg = <0x70>;
    	};
    };
    
    &pinctrl {
    	i2c1_default: i2c1_default{
    		group1 {
    			psels = <NRF_PSEL(TWIM_SDA, 0, 35)>,
    				<NRF_PSEL(TWIM_SCL, 0, 34)>;
    		};
    	};
    
    	i2c1_sleep: i2c1_sleep{
    		group1 {
    			psels = <NRF_PSEL(TWIM_SDA, 0, 35)>,
    				<NRF_PSEL(TWIM_SCL, 0, 34)>;
    			low-power-enable;
    		};
    	};
    };
    
    

    nrf5340_tricca_board.dtsi

    &pinctrl {
    	i2c1_default: i2c1_default {
    		group1 {
    			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
    				<NRF_PSEL(TWIM_SCL, 1, 3)>;
    		};
    	};
    
    	i2c1_sleep: i2c1_sleep {
    		group1 {
    			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
    				<NRF_PSEL(TWIM_SCL, 1, 3)>;
    			low-power-enable;
    		};
    	};
    
    	uart0_default: uart0_default {
    		group1 {
    			psels = <NRF_PSEL(UART_TX, 0, 20)>,
    				<NRF_PSEL(UART_RTS, 0, 19)>;
    		};
    		group2 {
    			psels = <NRF_PSEL(UART_RX, 0, 22)>,
    				<NRF_PSEL(UART_CTS, 0, 21)>;
    			bias-pull-up;
    		};
    	};
    
    	uart0_sleep: uart0_sleep {
    		group1 {
    			psels = <NRF_PSEL(UART_TX, 0, 20)>,
    				<NRF_PSEL(UART_RX, 0, 22)>,
    				<NRF_PSEL(UART_RTS, 0, 19)>,
    				<NRF_PSEL(UART_CTS, 0, 21)>;
    			low-power-enable;
    		};
    	};
    
    	uart1_default: uart1_default {
    		group1 {
    			psels = <NRF_PSEL(UART_TX, 1, 1)>;
    		};
    		group2 {
    			psels = <NRF_PSEL(UART_RX, 1, 0)>;
    			bias-pull-up;
    		};
    	};
    
    	uart1_sleep: uart1_sleep {
    		group1 {
    			psels = <NRF_PSEL(UART_TX, 1, 1)>,
    				<NRF_PSEL(UART_RX, 1, 0)>;
    			low-power-enable;
    		};
    	};
    
    };
    
    

  • DubiousDooby said:
    I went through the dts files of the semi-working project (the one where some of the pins don't work) to create the files.

    Maybe try to get inspiration from our DK boardfiles also? https://github.com/nrfconnect/sdk-zephyr/tree/main/boards/arm

    Can you zip and upload your whole "nrf5340_tricca_board/" directory, so I can have a look at all of it?

  • Hello and thanks for your patience. I redid the files and tried to take inspiration from the DK boardfiles you linked. I'm getting a similar but different error. It's complaining about not being able to find sram0. It's probably a bad sign that I have to mess with memory so I stopped once I got the following error.

     *  Executing task: nRF Connect: Build [pristine]: blinkysupreme/build (active) 
    
    Building blinkysupreme
    /bin/sh -c west build --build-dir /home/james/org/work/nrf/ncs_projects/blinkysupreme/build /home/james/org/work/nrf/ncs_projects/blinkysupreme --pristine --board tricca_tritant_v1 --no-sysbuild -- -DNCS_TOOLCHAIN_VERSION:STRING="NONE" -DBOARD_ROOT:STRING="/home/james/ncs/v2.1.0/zephyr/boards/arm;/home/james/ncs/v2.4.0/zephyr" -DCONFIG_DEBUG_OPTIMIZATIONS:STRING="y" -DCONFIG_DEBUG_THREAD_INFO:STRING="y" -DDTC_OVERLAY_FILE:STRING="/home/james/org/work/nrf/ncs_projects/blinkysupreme/tricca_tritant_v1.overlay" -DCONF_FILE:STRING="/home/james/org/work/nrf/ncs_projects/blinkysupreme/prj.conf"
    
    -- west build: generating a build system
    Loading Zephyr default modules (Zephyr base).
    -- Application: /home/james/org/work/nrf/ncs_projects/blinkysupreme
    -- CMake version: 3.20.5
    -- Found Python3: /home/james/ncs/toolchains/1f9b40e71a/usr/local/bin/python3.8 (found suitable exact version "3.8.2") found components: Interpreter 
    -- Cache files will be written to: /home/james/.cache/zephyr
    -- Zephyr version: 3.3.99 (/home/james/ncs/v2.4.0/zephyr)
    -- Found west (found suitable version "1.0.0", minimum required is "0.7.1")
    -- Board: tricca_tritant_v1
    -- Found host-tools: zephyr 0.16.0 (/home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk)
    -- Found toolchain: zephyr 0.16.0 (/home/james/ncs/toolchains/1f9b40e71a/opt/zephyr-sdk)
    -- Found Dtc: /home/james/ncs/toolchains/1f9b40e71a/usr/bin/dtc (found suitable version "1.4.7", minimum required is "1.4.6") 
    -- Found BOARD.dts: /home/james/ncs/v2.4.0/zephyr/boards/arm/tricca_tritant_v1/tricca_tritant_v1.dts
    -- Found devicetree overlay: /home/james/org/work/nrf/ncs_projects/blinkysupreme/tricca_tritant_v1.overlay
    devicetree error: /ipc/ipc0: undefined node label 'sram0_shared'
    -- In: /home/james/org/work/nrf/ncs_projects/blinkysupreme/build/zephyr, command: /home/james/ncs/toolchains/1f9b40e71a/usr/local/bin/python3.8;/home/james/ncs/v2.4.0/zephyr/scripts/dts/gen_defines.py;--dts;/home/james/org/work/nrf/ncs_projects/blinkysupreme/build/zephyr/zephyr.dts.pre;--dtc-flags;'';--bindings-dirs;/home/james/ncs/v2.4.0/nrf/dts/bindings;/home/james/ncs/v2.4.0/zephyr/dts/bindings;--header-out;/home/james/org/work/nrf/ncs_projects/blinkysupreme/build/zephyr/include/generated/devicetree_generated.h.new;--dts-out;/home/james/org/work/nrf/ncs_projects/blinkysupreme/build/zephyr/zephyr.dts.new;--edt-pickle-out;/home/james/org/work/nrf/ncs_projects/blinkysupreme/build/zephyr/edt.pickle;--vendor-prefixes;/home/james/ncs/v2.4.0/nrf/dts/bindings/vendor-prefixes.txt;--vendor-prefixes;/home/james/ncs/v2.4.0/zephyr/dts/bindings/vendor-prefixes.txt
    CMake Error at /home/james/ncs/v2.4.0/zephyr/cmake/modules/dts.cmake:276 (message):
      gen_defines.py failed with return code: 1
    Call Stack (most recent call first):
      /home/james/ncs/v2.4.0/zephyr/cmake/modules/zephyr_default.cmake:115 (include)
      /home/james/ncs/v2.4.0/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:66 (include)
      /home/james/ncs/v2.4.0/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:92 (include_boilerplate)
      CMakeLists.txt:4 (find_package)
    
    
    -- Configuring incomplete, errors occurred!
    FATAL ERROR: command exited with status 1: /home/james/ncs/toolchains/1f9b40e71a/usr/local/bin/cmake -DWEST_PYTHON=/home/james/ncs/toolchains/1f9b40e71a/usr/local/bin/python3.8 -B/home/james/org/work/nrf/ncs_projects/blinkysupreme/build -GNinja -DBOARD=tricca_tritant_v1 -DNCS_TOOLCHAIN_VERSION:STRING=NONE '-DBOARD_ROOT:STRING=/home/james/ncs/v2.1.0/zephyr/boards/arm;/home/james/ncs/v2.4.0/zephyr' -DCONFIG_DEBUG_OPTIMIZATIONS:STRING=y -DCONFIG_DEBUG_THREAD_INFO:STRING=y -DDTC_OVERLAY_FILE:STRING=/home/james/org/work/nrf/ncs_projects/blinkysupreme/tricca_tritant_v1.overlay -DCONF_FILE:STRING=/home/james/org/work/nrf/ncs_projects/blinkysupreme/prj.conf -S/home/james/org/work/nrf/ncs_projects/blinkysupreme
    

    tricca_tritant_v1.zip

  • sram0_shared is defined in ncs/zephyr/boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dts

    And this file is somehow not included in your board files.
    I have looked a bit at them, but have not yet been able to figure out what is missing.
    However, with some searching for filenames should yield you how this is included.

    I will go on vacation next week, so if you continue this case, one of my colleagues will take over the supporting

  • Thanks mate. I've gone through the files to compile the missing definitions regarding sram and ipc. Basically, I went through the includes for the dev kit and added the missing memory definitions to my custom . This led me to get the same error that I got last time I did this. That problem was solved by putting CONFIG_PINCTRL=y in my proj.conf. If possible, I'd like a bit of background as to why this setting is needed. I can now compile code and upload it to my custom board.

    Unfortunately this did not solve my issue with enabling pins P0.0, P0.1, P0.2, P0.03 and P0.19 as GPIO, and this is despite having the settings to disable them (see above in initial post). I verified this with an oscilloscope and running code similar to that below. I've also included my zipped board files. Hope this helps, and please let me know what I can provide or read to help. Thanks again.

    /*
     * Copyright (c) 2016 Intel Corporation
     *
     * SPDX-License-Identifier: Apache-2.0
     */
    
    #include <zephyr/kernel.h>
    #include <zephyr/drivers/gpio.h>
    
    /* 1000 msec = 1 sec */
    #define SLEEP_TIME_MS   1000
    #define SERV0_NODE DT_NODELABEL(serv0)
    #define EX10_NODE DT_NODELABEL(ex10)
    static const struct gpio_dt_spec serv0_dev = GPIO_DT_SPEC_GET_OR(SERV0_NODE, gpios, {0});
    static const struct gpio_dt_spec ex10 = GPIO_DT_SPEC_GET_OR(EX10_NODE, gpios, {0});
    
    int main(void)
    {
    	int ret;
    
    	if (!gpio_is_ready_dt(&serv0_dev)) {
    		return 0;
    	}
    
    	if (!gpio_is_ready_dt(&ex10)) {
    		return 0;
    	}
    
    	ret = gpio_pin_configure_dt(&serv0_dev, GPIO_OUTPUT_ACTIVE);
    	if (ret < 0) {
    		return 0;
    	}
    
    	ret = gpio_pin_configure_dt(&ex10, GPIO_OUTPUT_ACTIVE);
    	if (ret < 0) {
    		return 0;
    	}
    
    	while (1) {
    		ret = gpio_pin_toggle_dt(&serv0_dev);
    		if (ret < 0) {
    			return 0;
    		}
    		ret = gpio_pin_toggle_dt(&ex10);
    		if (ret < 0) {
    			return 0;
    		}
    		k_msleep(SLEEP_TIME_MS);
    	}
    	return 0;
    }

    // Copyright (c) 2023 Nordic Semiconductor ASA
    // SPDX-License-Identifier: Apache-2.0
    
    /dts-v1/;
    #include <nordic/nrf5340_cpuapp_qkaa.dtsi>
    #include "tricca_tritant_v1.dtsi"
    
    / {
    	model = "tricca-tritant-v1";
    	compatible = "tricca-technologies-inc-,tricca-tritant-v1";
    
    	chosen {
    		zephyr,sram = &sram0;
    		zephyr,flash = &flash0;
    		zephyr,code-partition = &slot0_partition;
    		/* shared memory reserved for the inter-processor communication */
    		zephyr,ipc_shm = &sram0_shared;
    	};
    
    	reserved-memory {
    		#address-cells = <1>;
    		#size-cells = <1>;
    		ranges;
    
    		sram0_image: image@20000000 {
    			/* Zephyr image(s) memory */
    		};
    
    		sram0_s: image_s@20000000 {
    			/* Secure image memory */
    		};
    
    		sram0_ns: image_ns@20040000 {
    			/* Non-Secure image memory */
    		};
    
    		sram0_shared: memory@20070000 {
    			/* SRAM allocated to shared memory */
    			reg = <0x20070000 0x10000>;
    		};
    	};
    
    };
    
    &flash0 {
    	partitions {
    		compatible = "fixed-partitions";
    		#address-cells = <1>;
    		#size-cells = <1>;
    
    		boot_partition: partition@0 {
    			label = "mcuboot";
    			reg = <0x0 0x10000>;
    		};
    		slot0_partition: partition@10000 {
    			label = "image-0";
    			reg = <0x10000 0x40000>;
    		};
    		slot0_ns_partition: partition@50000 {
    			label = "image-0-nonsecure";
    			reg = <0x50000 0x30000>;
    		};
    		slot1_partition: partition@80000 {
    			label = "image-1";
    			reg = <0x80000 0x40000>;
    		};
    		slot1_ns_partition: partition@c0000 {
    			label = "image-1-nonsecure";
    			reg = <0xc0000 0x30000>;
    		};
    		scratch_partition: partition@f0000 {
    			label = "image-scratch";
    			reg = <0xf0000 0xa000>;
    		};
    		storage_partition: partition@fa000 {
    			label = "storage";
    			reg = <0xfa000 0x6000>;
    		};
    	};
    };
    
    &gpio0 {
    	status = "okay";
    };
    
    &gpio1 {
    	status = "okay";
    };
    
    &i2c1 {
    	compatible = "nordic,nrf-twim";
    	status = "okay";
    	pinctrl-0 = <&i2c1_default>;
    	pinctrl-1 = <&i2c1_sleep>;
    	pinctrl-names = "default", "sleep";
    };
    
    /*
     * Copyright (c) 2019-2020 Nordic Semiconductor ASA
     *
     * SPDX-License-Identifier: Apache-2.0
     */
    
    /*
     * Default Flash planning for nrf5340dk_nrf5340 CPUAPP (Application MCU).
     *
     * Zephyr build for nRF5340 with ARM TrustZone-M support,
     * implies building Secure and Non-Secure Zephyr images.
     *
     * Secure image will be placed, by default, in flash0
     * (or in slot0, if MCUboot is present).
     * Secure image will use sram0 for system memory.
     *
     * Non-Secure image will be placed in slot0_ns, and use
     * sram0_ns for system memory.
     *
     * Note that the Secure image only requires knowledge of
     * the beginning of the Non-Secure image (not its size).
     */
    
    &slot0_partition {
    	reg = <0x00010000 0x40000>;
    };
    
    &slot0_ns_partition {
    	reg = <0x00050000 0x30000>;
    };
    
    &slot1_partition {
    	reg = <0x00080000 0x40000>;
    };
    
    &slot1_ns_partition {
    	reg = <0x000c0000 0x30000>;
    };
    
    /* Default SRAM planning when building for nRF5340 with
     * ARM TrustZone-M support
     * - Lowest 256 kB SRAM allocated to Secure image (sram0_s)
     * - Middle 192 kB allocated to Non-Secure image (sram0_ns)
     * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
     *   (see nrf5340_shared_sram_planning_conf.dts)
     */
    &sram0_image {
    	reg = <0x20000000 DT_SIZE_K(448)>;
    };
    
    &sram0_s {
    	reg = <0x20000000 0x40000>;
    };
    
    &sram0_ns {
    	reg = <0x20040000 0x30000>;
    };
    

    1732.tricca_tritant_v1.zip

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