I2S first and second cycle data is not available, causing a problem with the level.

[stars]

Hi,

I used the example in SDK_17.1 and NRF52DK board to test I2S.

The logical analysis instrument picked up the following waveform:

As you can see, the data was initially absent, causing a problem with the data input pin level on the I2S hardware I plugged in. What I want to know is how I should configure the data to be transferred from the very beginning.

Best regards,

Stars

[JONATHAN LL]

HI,

What changes have you made to the example? 

What bit rate are you using?

We have info on use and configuration information here https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/i2s.html?cp=5_2_0_43#concept_z2v_24y_vr . 

Regards,
Jonathan

[stars]

Hi，

I used the default example and didn't make any changes. The requirement is that you want the data to be synchronized with the clock. Can you reproduce the phenomenon using nrf52DK?

For example, there is no data in the red circled part of the picture. I want the data to appear with the clock. Is that even possible? Or my understanding of I2S is wrong, I2S communication, the first part of the data and the clock is not synchronized?

Best regards,

Stars

[stars]

Hi，

After testing, the correct data can be obtained if a wire is added directly to the logic analyzer and the three output pins of the I2S.

We suspect a parasitic capacitor on the wire is making the data normal, but why is that?

Can you give me some advice on screening?

Best regards,

Stars

[JONATHAN LL]

Thanks for providing all the details but I would like to have the option to reproduce the issues.

Can you provide a minimal sample that produces the issue?


How many board do you have that exhibit the "bad" behavior. 


Are you able to switch the SoC from a "bad" board to a good one? this will help eliminate if there is any issues with the PCB. 

Regards,
Jonathan

[stars]

Hi，

Now in the research and development stage, the second batch of half of the board has a problem, we want to determine the problem, otherwise this is a fatal problem in the batch. I'm on the third batch of boards, not sure if we'll have the same problem.

There are chip exchange tests, it can be determined that this phenomenon is followed by the board. It is normal to replace the chip data on the wrong board on the normal board.

Best regards,

Stars

[JONATHAN LL]

stars said:

There are chip exchange tests, it can be determined that this phenomenon is followed by the board.

Does that mean that the board is the cause for the error? is that what you are saying?

Regards,
Jonathan

[stars]

Hi，

Yes, the circuit board caused the cause, but do not know what the specific reason is, because now increase the length of the wire data is normal. We can't understand how it works. What causes right channel data to overwrite left channel data

Best regards,

Stars

[JONATHAN LL]

Hi Stars, 

stars said:

What causes right channel data to overwrite left channel data

I am not sure but it could be related to the ERRATA 54: https://infocenter.nordicsemi.com/topic/errata_nRF52832_Rev3/ERR/nRF52832/Rev3/latest/anomaly_832_54.html?cp=5_2_1_0_1_6 

When using Aligned mode left and right samples are swapped. 



So to summarize:
you have a product\deice that is a PCB that has the nRF52832 mounted and you are using I2S. 
- There is an issue with the I2S signal, the cause seems to be from the PCB(?), so it is not SoC related. 
- increasing the length of debug wires solves the signal issue seen on I2S.
- The issue is that the Right cannel overwrites the Left channel data. 


Regards,
Jonathan