Reset pin behaviour

[Fennec]

On both the 51 and the 52, I believe the reset pin is active low, and should otherwise be tied to VDD?

The reason I am asking is that I failed to find this information specifically pointed out in the documentation. If I'm missing something, please point out under which section I could find this in the reference manuals for either of these products.

Thanks a tonne for your time. :)

[atune]

Yes it's active low. In addition the internal pull-up should be enabled when a pin is configured as a reset pin. (disclaimer: idk about nrf51 earlier revisions)

It's funny that it's not explicitly stated anywhere. The only real reference (at least in 52's case) to the fact is in p.100 of the nRF52 OPS

which implies that a) pulling the pin down resets the chip and b) the internal pullup is enabled (R = 13kOhm).

[David McIntosh]

To clarify: For the nRF52840:

1. The firmware doesn't have to enable internal pull-up when the pin reset is configured

2. The off-chip HW does not need to include a pull-up resistor. (Note: For  improved noise immunity some may choose to lower the pull-up resistance)

3. The pull-up resistance is about 13kOhm (same pull-up HW as all other GPIO). nRF52840 PS 1.1 doesn't have this note about 5 time constants (5xtau).