Noise on PCB during 2.4GHz RF transmission

[MinhDuc]

Hello friends, 

I am using nrf52840-CKAA for my customize PCB. 

I am facing the noise during RF transmission on my ADC. The peak noise happen when I send a packet of data via RF antenna. 

Power_Tx = 4dBm

 

When I decrease the Tx Power to -12dBm, the peak noise was gone.

I wonder that MCU takes a lot of power during RF transmission so it affect to the stability of power line. 

In nrf52840-CKAA, currently I tie all VSS pin together instead of tie each of them directly to the GND plane. Is it the problem? 

I appreciate all your suggestions. 

Minhduc

[Simonr]

Hi

Can you share your HW files so we can do a review of schematics and the PCB you're using? Here is an image of how the ground plane and VSS pins should be connected. 

Also, please share some more details on the ADC you're using. What are you measuring on it, and what is this external ADC exactly? And is it connected to the nRF52840 somehow? If so, to what pins on the nRF52840.

Best regards,

Simon

[MinhDuc]

Hi Simonr, 

My ADC is Intan chip RHS2116. It is controlled by MCU via SPI communication. 

Instead of connecting all VSS at top layer ground plan, I use uVia for each VSS pin for connecting it directly to the layer 2 ground plane. 

In my PCB, I use a lot of via so it limit the return path. Do you think it is a possible reason? 

Best regards,

[hmolesworth]

Common problem, the nRF VDD sags a lot during BLE transmission which (worse) is often asynchronous to the ADC readings. One fix is to feed the supply for the external ADC via an ideal diode, thus when the nRF VDD sags the external ADC VDD holds up with a more-or-less linear droop for the duration of the nRF VDD sag; this droop is orders of magnitude less than nRF VDD sag so does not have a big impact on ADC readings. A separate regulator which blocks reverse-drain can also be used instead of the ideal diode.

[MinhDuc]

Hello hmolesworth,

Yes I think it makes sense. 

In the case of ideal diode, should I use each diode for each VDD pin of external ADC? 

Best,

[hmolesworth]

I would just common the ADC VDD pins and drive from a single Ideal Diode; it is not clear which VDD pin supplies which subsystem within the ADC die, often one is used for io and others for analogue but it doesn't matter here I don't think. Capacitor should be (say) 47uF 6.3V or (better) 10V or 16V rating. Normally connect EN to Vdd (ie nRF VDD) or leave floating (EN has internal pull-up). Note "It is not necessary (or recommended) to use separate “analog” and “digital” power lines."

VSTIM would perhaps be treated separately if also coming from nRF VDD.

[MinhDuc]

It was very clear. I don't have experience using ideal diode for this purpose. Can you please recommend which one is better for my case? Ideal diode or separate LDO? 

Appreciate your help. 

[hmolesworth]

If using a battery with plenty of capacity, such as a rechargeable battery or AA cells, or external supply such as USB, then the average VDD voltage probably stays high enough for 3.3 volt operation and so use the ideal diode (small, cheap, low voltage drop 30mV). If using (say) CR2032 or CR2540 coin cells where the voltage will drop over time to (say) 2.7 volts, then a buck-boost regulator to supply the ADC with 3.3 volts becomes mandatory. If using such a buck-boost regulator to maintain 3.3 volts for the ADC, choose one which will hold the voltage output even when the input voltage sags or drops sharply. Something like a TPS63000; there are lots of options but I use this one. TPS63000 in which case this replaces the Ideal Diode.

How are you handling the 32-bit SPI transfer /CS requirement other than millions of short transfers? "The CS line must be pulsed high between every 32-bit data transfer.; ie. /CS stays high for 154 ns between words"

[MinhDuc]

Thank you for sharing. 

My SPI is ok. It’s around 1.5us CS pulse high between each 32-bit SPI command.

[hmolesworth]

I was thinking more of high transfer rate with long DMA transfers to get predictably even sampling, given that the radio requires interrupt priority short transfers do not work well and lead to unpredictable sampling unless scheduled away from radio activity. Something like the STM32U535xx; For the nRF5x PWM spoofing of SCK, MOSI and /CS works in conjunction with using SPIS instead of SPIM to receive the data but the frequency is on the low side. Spoofing of SCK, MOSI and /CS with PPI-linked timers is also an option, but increases power due to the significant number of peripherals running and synchronising the timers requires care. What data rate do you achieve?