Problem identifying which GPIO is the cause for waking the MCU out of "system off" mode

[Tsahi Holand]

Hi,

In my design, I have a push-button that pulls low when pressed and remains floating otherwise. This button is used to wake the nRF52832 from system off mode.

The push-button is connected to P0.11 which is configured as input with an internal pull-up. P0.11 is also configured to sense the input signal.

Additionally, I’m also using other GPIOs to wake the MCU from system off mode.

The issue I’m facing is as follows:

When a different GPIO (other than P0.11) wakes the MCU from system off mode and a reset occurs, the P0.11 pin is reset and no longer maintains its pull-up configuration. Instead, the signal is pulled low (though I’m not entirely sure why), which activates a latch even though the push-button wasn’t pressed.

I might have misunderstood the sequence of events.

Any help would be greatly appreciated.

Thanks!

[snoopy20]

It's not floating, it's a weak high. The weak pullup configuration is reset upon system reset and then it's floating.

Ensure you're disabling the input buffer for all pins you don't need it on.

Ensure the NFC pins are disabled if you are intending to use those pins as GPIO. I can't recall which two pins they are but think they are 12 and 13 (I use 810 which doesn't have them).

Ensure you are setting the state of the pin (pull-up high) before enabling sense, not as one statement which is the obvious way to do it, otherwise they may race (sense fires before pull-up has enabled or pulled the pin high if there's some capacitance on it etc).

With these actions done then if behaviour still isn't correct

Take at the RESETREA to see why the CPU is resetting, if that's still an issue.
Take a look at the LATCH values in GPIO to see which ones are firing.

Regards,

Andrew

[Tsahi Holand]

Thank you Andrew for your reply.

I seem to have found the cause of the problem although I have no idea why this happens:

Please consider the following sequence of events:

- 2 GPIOs (P0.11 and P0.26) are configured as pullup

- 2 GPIOs (P0.11 and P0.26) are configured to sense low

- 2 GPIOs (P0.11 and P0.26) latch is cleared

- sd_power_system_off() is called

- After 10 seconds the P0.26 pin is pulled low by an external RTC (latch is triggered)

- For some reason P0.11 is also pulled low and so latch is also triggered

This happens only if the J-link RTT viewer is connected ?!

When the viewer is disconnected the GPIOs behave as expected:

Maybe you can shed some light?

Thanks,

Tsahi

[Kenneth]

Likely related to this:
https://docs.nordicsemi.com/bundle/errata_nRF52832_Rev3/page/ERR/nRF52832/Rev3/latest/anomaly_832_81.html#anomaly_832_81

Kenneth

[snoopy20]

I would say so as well. I've not had to deal with that errata.

The wonderful thing about the NRF52 series is there's always a workaround. Can you live with it for debug mode? Assuming not...

Both pins are going to pull low but there'll be a slight timing difference which you can use.

Complete hardware based solution...

Wire both pins to GPIOTE.

Then pass those events to two PPI's each wired into a separate PPI_GRP. Use the Fork on each PPI to disable the opposite group.

Now also wire each PPI to the EGU using different event channels. Enable the interrupt.

Now you'll get one interrupt and can look at the EGU events to know which pin actually fired.

Reset the GPIO configs to deal with the errata, clear the PPI events and enable both PPI groups to start over.